參數(shù)資料
型號(hào)： ZR36504
廠商： Electronic Theatre Controls, Inc.
英文描述： Video & Audio Interface solution via USB
中文描述： 視頻
文件頁(yè)數(shù)： 42/74頁(yè)
文件大小： 298K
代理商： ZR36504
ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
November-99
Page 42 of 42
D4-D0: Pix_Depth (number of bits per pixel). These bits should be
ignored in compressed data frames.
Unsigned Word integer - number of pixels per line.
Unsigned Word integer - number of lines in frame.
8
10
Frame_Width
Frame_Height
2
2
5.
DRAM Control and Interface
The ZR36504 requires an external 16bit x 256K DRAM to operate (VGA cameras require
a 16bit x 1024K DRAM to provide 15f/s). The DRAM operation voltage must be 3.3v,
and its access time must be 60nS or less. The ZR36504 uses the Fast-Page-Read and Fast-
Page-Write DRAM access modes only. Refresh cycles are automatically inserted between
Read or Write bursts by the ZR36504.
The ZR36504 allocates two ranges of memory addresses in the external DRAM, that are
regarded as memory buffers:
Video Output data buffer. The ZR36504 uses this buffer as a FIFO, to store output
data from its compressor (in the Compressed video mode) or from its scaler (in the Raw
video mode). Previously written data is read to be sent to host computer via USB
transfers (End-Point 2).
Video Frame Delay Line buffer. This buffer is used in the Compressed Video mode
only. The ZR36504 uses this buffer as a huge FIFO, to store the current reconstructed
frame. The compressor always needs to read the previous reconstructed frame as a
reference image in the Compression Video mode.
Each of these buffers is assigned a Start-Address and an End-Address (which relate to the
physical 20-bit address-space 0x00000-0xFFFFF of the DRAM). These addresses are
supposed to be defined by the ZR36504 software driver as a part of the video stream
initialization. The following registers of the ZR36504 are used to set the addresses of the
two buffers:
Parameter
Register
address
DRAM_SIZE
Reg.18/d1
'0': Selects 4Mbit DRAM (16bit x 256K)
'1': Selects 16Mbit DRAM (16bit x 1024K)
DRM_COL_SLCT
Reg.18/d7
Defines address bit a19 for end of Video Output
data buffer if 16Mbit DRAM used. This
parameter is used as an extension for
UR_LST_ROW and VDW_LST_ROW.
UR_1ST_ROW [9..0]
Reg.18/d5,
Reg.19/d0,
Reg.20/d7-d0
always '0' (start of a DRAM row). The bit a19
is also always '0'.
UR_LST_ROW [9..0]
Reg.18/d6,
Reg.19/d1,
Read. Only a18..a9 are specified, a8..a0 are
Usage
Start Address of Video Output data buffer for
Read. Only a18..a9 are specified, a8..a0 are
End Address of Video Output data buffer for
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