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參數(shù)資料
| 型號： | ZR36016 |
| 廠商： | Zoran Corporation |
| 英文描述： | JPEG Pre- and Post-Processor(JPEG 先-后處理器) |
| 中文描述： | JPEG格式前和后處理器（JPEG格式先-后處理器） |
| 文件頁數(shù)： | 6/36頁 |
| 文件大?。?/td> | 228K |
| 代理商： | ZR36016 |
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6
Integrated Color Space / Raster-To-Block Converter
Bit 2
SBFL:
Image format conversion filter.
Initial Value = 0.
0=Selects simple decimation or interpolation without
filtering.
1=Selects decimation or interpolation of color compo-
nents with filter processing.
This bit controls filtering in Format Converter #1.
Bit 3
DSFL:
sion filter.
PXIN/OUT bus data image format conver-
Initial Value = 0.
0=Selects simple decimation or interpolation without
filtering.
1=Selects decimation or interpolation of color compo-
nents with filter processing.
This bit controls filtering in Format Converter #2.
Bit 4
HRFL:
tion filter.
Half-size horizontal decimation or interpola-
Initial Value = 0.
0=Selects simple half-size horizontal decimation or in-
terpolation without filtering.
1=Selects decimation or interpolation with filtering.
Must be used only with HORZ = 1.
Bit 5
HORZ:
interpolation.
Half-size horizontal decimation or
Initial Value = 0.
0=Selects no horizontal decimation nor interpolation.
1=Selects half-size horizontal decimation on compres-
sion, and interpolation on expansion. The
decimated data stream is loaded in the strip buffer
on compression, and the data before interpolation
is loaded on expansion. The decimation and inter-
polation are performed on Y, Cr and Cb, or on Y
only, depending on the MODE field.
Bit 6
VERT:
Half-size vertical decimation or interpolation.
Initial Value = 0.
0=Selects no vertical decimation nor interpolation.
1=Selects half-size vertical decimation (by line drop-
ping) in compression or interpolation by line
replication in expansion. The decimated data
stream is loaded in the strip buffer on compression,
and the data before interpolation is loaded on ex-
pansion. The lines dropped in decimation are the
second, fourth,… lines of the active window. This bit
does not apply to the 4:1:1(H2V2) format.
Bit 7
CKRT:
half-size horizontal decimation/interpolation.
Ratio of PXCLK to SYSCLK frequency, with
Initial Value = 0.
0=Selects normal PXCLK to SYSCLK frequency ratio
when HORZ = 1.
1=Selects slow SYSCLK (doubles the PXCLK to SY-
SCLK frequency ratio) when HORZ = 1.
This bit selects the PXCLK to SYSCLK frequency
ratio, when HORZ = 1 (horizontal half-size mode). It
optionally allows the SYSCLK rate to be halved rel-
ative to its rate with full horizontal size. See Table 8.
Setup Register 1 (Continued)
The NAX, PAX, NAY and PAY registers define the offset and
dimensions of the active area. See also Figure 4.
Setup Register 2
Read/Write
Indirect address: 0x01
Initial Value
0x00
Bit 0
YMCS:
RGB or YeMaCy selection.
Initial Value = 0.
0=RGB.
1=YeMaCy. The ZR36016 treats RGB as YeMaCy
when the image format on the PXIN/PXOUT buses
are RGB in the MODE field.
Bit 1
SIGN:
Signed values of Cr and Cb.
Initial Value = 0.
Selects the sign convention of Cr and Cb on the
PXIN bus input and the output on the PXOUT bus.
0=Offset binary (unsigned).
1=2's complement signed.
The data transfers with the ZR36050 are always
unsigned. This bit is not used when MODE = 0x19
(4:4:4:4).
Bit 2
CCIR:
When the color space conversion is done, the signal
levels can be as specified in CCIR601 or full scale.
This bit is not used when MODE = 0x19 (4:4:4:4).
CCIR signal level selection. Initial Value = 0.
0=8 bits full scale.
1=CCIR R601.2 standard levels.
Bit 3-5
Reserved.
Bit 6
SYEN:
Function selection for PXOE.
Initial Value = 0.
0=Tri-stating of PXOUT bus, HOUT and VOUT are
controlled by PXOE.
1=Only the PXOUT bus is three-stated by PXOE.
Bit 7
Reserved.
Window Area Register NAX-Lo
Read/Write
Indirect address: 0x02
Initial Value
0x00
Bits 0-7
NAX(7:0):
edge of HIN to the starting point of the active
window area (X-axis offset). Lower 8 bits.
The number of pixels from the rising
Initial Value = 0.
7
6
5
4
3
2
1
0
–
SYEN
–
–
–
CCIR
SIGN
YMCS
7
6
5
4
3
2
1
0
NAX[7:0]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZR36050 | JPEG Image Compression Processor(JPEG 圖象壓縮處理器) |
| ZR36060 | Integrated JPEG Codec(集成JPEG編解碼器) |
| ZR36060 | Circular Connector; No. of Contacts:19; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Cable Receptacle; Insert Arrangement:14-19 |
| ZR36060PQC | Integrated JPEG CODEC |
| ZR36067 | AV PCI CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZR36016PQC | 制造商:ZORAN 功能描述: |
| ZR36016PQC-30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:INTEGRATED COLOR SPACE / RASTER-TO-BLOCK CONVERTER |
| ZR36050 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:JPEG IMAGE COMPRESSION PROCESSOR |
| ZR36050PQC-21 | 制造商:ZORAN 功能描述: |
| ZR36050PQC27 | 制造商:ZORAN 功能描述:* |
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