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參數(shù)資料
| 型號： | ZR36016 |
| 廠商： | Zoran Corporation |
| 英文描述： | JPEG Pre- and Post-Processor(JPEG 先-后處理器) |
| 中文描述： | JPEG格式前和后處理器（JPEG格式先-后處理器） |
| 文件頁數(shù)： | 10/36頁 |
| 文件大小： | 228K |
| 代理商： | ZR36016 |
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10
Integrated Color Space / Raster-To-Block Converter
Hardware Interfaces
Image Input/Outputs
SYSCLK and PXCLK
The ZR36016 requires two system clocks: PXCLK, at the data
rate of the pixel buses, and SYSCLK, at the data rate of the
ZR36050 interface. The frequency ratio of PXCLK to SYSCLK
depends on the compressed image format and other setup
register bits, as shown in Table 8.
For some of the configurations shown in the table, the PXCLK to
SYSCLK frequency ratio is 1. When this happens, the output
pixel bus, PXOUT, is actually clocked with SYSCLK. PXCLK, at
the same rate as SYSCLK, is still required, however, to clock the
input pixel bus PXIN, and for reset and other operations.
When the HORZ setup register bit is set, for horizontal decima-
tion or interpolation, there are in most cases two options for the
PXCLK to SYSCLK frequency ratio as selected by the CKRT bit
of Setup Register 1.
1.
N
= Decimation/Interpolation is performed on these components; – = Not performed or not applicable.
Table 8: Ratio of PXCLK to SYSCLK
ZR36050 Image
Format
HORZ
VERT
Compression Format and
Resolution
PXCLK to SYSCLK
Frequency Ratio
Bit
Decimation/
Interpolation
[1]
CKRT
Y
CB/CR
0
1
4:2:2
1
N
N
1
2:1:1 (Quarter Screen)
1/2
1
4:2:2
1
N
N
0
2:1:1 (Horizontal Half-Screen)
1/2
1
4:2:2
0
–
–
1
4:2:2 (Vertical Half-Screen)
1/2
4:2:2
0
–
–
0
4:2:2 (Full-Screen)
1/2
4:1:1 (H4V1)
1
N
–
1
2:1:1 (Quarter Screen)
1/2
1
4:1:1 (H4V1)
1
N
–
0
2:1:1 (Horizontal Half-Screen)
1/2
1
4:1:1 (H4V1)
0
–
–
1
4:1:1 (Vertical Half-Screen)
1/2
4:1:1 (H4V1)
0
–
–
0
4:1:1 (Full-Screen)
1/2
4:1:1 (H2V2)
–
–
–
–
4:1:1 (Full-Screen)
1/2
4:4:4
1
Each Component
1
2:2:2 (Quarter Screen)
1/4
1/2
4:4:4
1
Each Component
0
2:2:2 (Horizontal Half-Screen)
1/4
1/2
4:4:4
0
–
–
1
4:4:4 (Vertical Half-Screen)
1/4
4:4:4
0
–
–
0
4:4:4 (Full-Screen)
1/4
4:4:4:4
1
Each Component
1
2:2:2:2 (Quarter Screen)
1/2
1
4:4:4:4
1
Each Component
0
2:2:2:2 (Horizontal Half-Screen)
1/2
1
4:4:4:4
0
–
–
1
4:4:4:4 (Vertical Half-Screen)
1/2
4:4:4:4
0
–
–
0
4:4:4:4 (Full-Screen)
1/2
4:0:0 (1:0:0)
1
N
–
1
2:0:0 (Quarter Screen)
1
4:0:0 (1:0:0)
1
N
–
0
2:0:0 (Horizontal Half-Screen)
1
4:0:0 (1:0:0)
0
–
–
1
4:0:0 (Vertical Half-Screen)
1
4:0:0 (1:0:0)
0
–
–
0
4:0:0 (Full-Screen)
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZR36050 | JPEG Image Compression Processor(JPEG 圖象壓縮處理器) |
| ZR36060 | Integrated JPEG Codec(集成JPEG編解碼器) |
| ZR36060 | Circular Connector; No. of Contacts:19; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Cable Receptacle; Insert Arrangement:14-19 |
| ZR36060PQC | Integrated JPEG CODEC |
| ZR36067 | AV PCI CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZR36016PQC | 制造商:ZORAN 功能描述: |
| ZR36016PQC-30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:INTEGRATED COLOR SPACE / RASTER-TO-BLOCK CONVERTER |
| ZR36050 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:JPEG IMAGE COMPRESSION PROCESSOR |
| ZR36050PQC-21 | 制造商:ZORAN 功能描述: |
| ZR36050PQC27 | 制造商:ZORAN 功能描述:* |
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