- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373821 > ZR36016 (Zoran Corporation) JPEG Pre- and Post-Processor(JPEG 先-后處理器) PDF資料下載
參數(shù)資料
| 型號： | ZR36016 |
| 廠商： | Zoran Corporation |
| 英文描述： | JPEG Pre- and Post-Processor(JPEG 先-后處理器) |
| 中文描述： | JPEG格式前和后處理器（JPEG格式先-后處理器） |
| 文件頁數(shù)： | 3/36頁 |
| 文件大小： | 228K |
| 代理商： | ZR36016 |
第1頁第2頁當前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
3
Integrated Color Space / Raster-To-Block Converter
SIGNAL DESCRIPTIONS
1. The state of the COMP pin determines the direction of the bidirectional pins BDATA, DSYNC, STOP, and EOS. When COMP is high (the ZR36050 is in compression
mode), BDATA, DSYNC and EOS are outputs and STOP is an input. When COMP is low (the ZR36050 is in expansion mode), BDATA, DSYNC and EOS are inputs
and STOP is an output.
Table 1: PIXEL Input/Output
Signal
I/O
Description
PXIN[23:0]
I
Pixel data input bus.
PXOUT[23:0]
O
Pixel data output bus.
PXOE
I
PXOUT bus output enable.
HIN
I
Horizontal input data enable. Rising edge indicates beginning of scan line and start of NAX and PAX counts. For
synchronization of PXIN.
VIN
I
Vertical input data enable. Rising edge indicates beginning of picture and start of NAY and PAY counts. For synchro-
nization of PXIN.
HOUT
O
Horizontal output data enable. Follows HIN by internal processing delay. For synchronization of PXOUT.
VOUT
O
Vertical output data enable. Follows VIN by internal processing delay. For synchronization of PXOUT.
PXEN
I
Pixel enable for PXIN and PXOUT. For discontinuous transfers.
Table 2: Host Interface
Signal
I/O
Description
ADD[1:0]
I
Internal registers address input.
DATA[7:0]
I/O
Internal registers data bus.
WR
I
Write enable to internal registers. Written to on rising edge.
RD
I
Read enable for internal registers.
CS
I
Chip select for host interface.
CBSY
I
CODEC busy. Indicates that the pixel side is ready to exchange strip buffers, but the ZR36050 side is not ready yet.
Table 3: Strip Buffer Memory Interface
Signal
I/O
Description
MDATA[15:0]
I/O
Memory data bus for strip buffer.
MADD[15:0]
O
Memory address for strip buffer.
MWE
O
Memory write enable for strip buffer.
MOE
O
Memory output enable for reading strip buffer.
Table 4: ZR36050 Interface
Signal
I/O
Description
BDATA[7:0]
I/O
Block data bus, connected to ZR36050 PIXEL bus.
DSYNC
I/O
Block data synchronization with ZR36050.
STOP
I/O
Data flow control with ZR36050.
EOS
I/O
End of scan control with ZR36050.
COMP
[1]
I
Compression/expansion mode indicator from ZR36050.
相關PDF資料 |
PDF描述 |
|---|---|
| ZR36050 | JPEG Image Compression Processor(JPEG 圖象壓縮處理器) |
| ZR36060 | Integrated JPEG Codec(集成JPEG編解碼器) |
| ZR36060 | Circular Connector; No. of Contacts:19; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Cable Receptacle; Insert Arrangement:14-19 |
| ZR36060PQC | Integrated JPEG CODEC |
| ZR36067 | AV PCI CONTROLLER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ZR36016PQC | 制造商:ZORAN 功能描述: |
| ZR36016PQC-30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:INTEGRATED COLOR SPACE / RASTER-TO-BLOCK CONVERTER |
| ZR36050 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:JPEG IMAGE COMPRESSION PROCESSOR |
| ZR36050PQC-21 | 制造商:ZORAN 功能描述: |
| ZR36050PQC27 | 制造商:ZORAN 功能描述:* |
發(fā)布緊急采購，3分鐘左右您將得到回復。