參數(shù)資料
型號(hào)： ZR36016
廠商： Zoran Corporation
英文描述： JPEG Pre- and Post-Processor(JPEG 先-后處理器)
中文描述： JPEG格式前和后處理器（JPEG格式先-后處理器）
文件頁數(shù)： 11/36頁
文件大?。?/td> 228K
代理商： ZR36016
11
Integrated Color Space / Raster-To-Block Converter
PXIN/PXOUT Bus Data Arrangement
The PXIN/PXOUT buses are 24 bits each. The 24 bits are
divided into 8-bit bytes, as follows.
PXIN/OUT[23:0]
MSB
LSB
23:16
MSB
LSB
15:8
MSB
LSB
7:0
The I/O arrangement is determined by the MODE and DSPY
fields, as shown below in Table 9. In this table, the 3 compo-
nents of (4:4:4), (4:2:2), (4:1:1), (1:0:0) formats are designated
(A:B:C), components of (4:4:4:4) format are designated
(A:B:C:D), and (A:B:C) corresponds with (R:G:B), (Y:Cb:Cr) or
(Cy:Ma:Ye). 1st, 2nd, etc., refer to the PXCLK time slots.
Table 9: I/O Bus Arrangements
PXINOUT
Bus
I/O Format
4:4:4
4:2:2
4:1:1
1:0:0
4:4:4:4
1st
2nd
1st
2nd
1st
2nd
3rd
4th
1st
2nd
1st
2nd
23-16
A
A
A
A
A
A
A
A
A
A
A
C
15-8
B
B
B
C
B[7:6]
/C[7:6]
B[5:4]
/C[5:6]
B[3:2]
/C[3:2]
B[1:0]
/C[1:0]
–
–
B
D
7-0
C
C
–
–
–
–
–
–
–
–
–
–
4:1:1 in Table 9 is the Philips H4V1 format. As shown in
Table 10, it uses only the upper 12-bits on the PXIN/PXOUT
buses.
Table 10: Philips 4:1:1 Format
PXIN/OUT
1st
2nd
3rd
4th
PXIN/OUT[23:16]
A[7:0]
A[7:0]
A[7:0]
A[7:0]
PXIN/OUT[15]
B[7]
B[5]
B[3]
B[1]
PXIN/OUT[14]
B[6]
B[4]
B[2]
B[0]
PXIN/OUT[13]
C[7]
C[5]
C[3]
C[1]
PXIN/OUT[12]
C[6]
C[4]
C[2]
C[0]
PXIN/OUT[11:0]
–
–
–
–
PXIN/PXOUT Delay
The image data which is input on the PXIN bus is output on the
PXOUT bus after an internal delay which depends on the MODE
field and HORZ bit of the registers. The delays of VIN to VOUT
and HIN to HOUT are the same as these. See Table 11 and
Figure 5.
1.
Where MD =
1 when MODE = 0x0, 0x4, 0x8 or 0xC and = 0 for all others.
Table 11: PXIN to PXOUT Delay
Configuration
MD
[1]
Delay in PXCLK Clock
Cycles (d)
HORZ
0
0
20
0
1
24
1
0
17
1
1
20
HIN
PXIN
n-3
n-2
n-1
n
0
1
d-3
d-2
d-1
d
d+1
d+2
d+3
Figure 5. PXIN/PXOUT Delay Timing
HOUT
PIXOUT
n-3-d
n-2-d
n-1-d
n-d
-d
1-d
n-2
n-1
n
0
1
2
3
n = number of PXCLKs in one full line (HSYNC to HSYNC)
相關(guān)PDF資料
PDF描述
ZR36050 JPEG Image Compression Processor(JPEG 圖象壓縮處理器)
ZR36060 Integrated JPEG Codec(集成JPEG編解碼器)
ZR36060 Circular Connector; No. of Contacts:19; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Cable Receptacle; Insert Arrangement:14-19
ZR36060PQC Integrated JPEG CODEC
ZR36067 AV PCI CONTROLLER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZR36016PQC 制造商:ZORAN 功能描述:
ZR36016PQC-30 制造商:未知廠家 制造商全稱:未知廠家 功能描述:INTEGRATED COLOR SPACE / RASTER-TO-BLOCK CONVERTER
ZR36050 制造商:未知廠家 制造商全稱:未知廠家 功能描述:JPEG IMAGE COMPRESSION PROCESSOR
ZR36050PQC-21 制造商:ZORAN 功能描述:
ZR36050PQC27 制造商:ZORAN 功能描述:*
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*