
13
Integrated Color Space / Raster-To-Block Converter
Data Representation
The results of color space conversion are limited and rounded to
8 bits. These results may be output with the full 256 levels or
reduced to 220 levels as specified by the CCIR R601.2 stan-
dard, by using the CCIR bit in Setup Register 2. The R,G,B and
Y values are always unsigned, but offset binary or 2’s comple-
ment representation may be selected for Cr and Cb signals by
the SIGN bit. These choices are shown in Table 12 and
Table 13.
Table 12: Data Representation With CCIR = 0
CCIR = 0
R, G, B, Y
Cr, Cb
SIGN = 0
Cr, Cb
SIGN = 1
Hex
Decimal
Unsigned
Offset Binary
2's Complement
0xFF
0xFE
:
0x81
0x80
0x7F
:
0x01
0x00
255
254
:
129
128
127
:
1
0
255
254
:
129
128
127
:
1
0
127
126
:
1
0
-1
:
-127
-128
-1
-2
:
-127
-128
127
:
1
0
Table 13: Data Representation With CCIR = 1
CCIR = 1
R, G, B, Y
Cr, Cb
SIGN = 0
Cr, Cb
SIGN = 1
Hex
Decimal
Unsigned
Offset Binary
2's Complement
0xFF
0xFE
:
0xF1
0xF0
:
0xEC
0xEB
:
0x91
0x90
:
0x81
0x80
0x7F
:
0x70
0x6F
:
0x10
0x0F
:
0x01
0x00
255
254
:
241
240
:
236
235
:
145
144
:
129
128
127
:
112
111
:
16
15
:
1
0
235
235
:
145
144
:
129
128
127
:
112
111
:
16
16
112
112
:
108
107
:
17
16
:
1
0
-1
:
-16
-17
:
-112
-112
-1
-2
:
-15
-16
:
-20
-21
:
-111
-112
-112
112
112
111
:
16
15
:
1
0
HIN and VIN
The following restrictions must be observed for the HIN signal.
The low interval (A in Figure 9) must be at least two PXCLK
cycles. In addition the total period must be an even number of
PXCLK cycles (B in Figure 9).
When PXEN is used to control the pixel data flow, the effective
number of PXCLK cycles is modified. Effective cycles are
counted only when PXEN is active, as illustrated in Figures 10
and 11.
The low interval of VIN must be at least 2 PXCLK cycles.
HIN
Figure 9. Restrictions for HIN
A
B
PXCLK
HIN
PXEN
Figure 10. Effective PXCLK Cycles (6 Effective Cycles)
1
2
3
4
5
6
“LOW”
PXCLK
HIN
PXEN
Figure 11. Effective PXCLK Cycles (4 Effective Cycles)
1
X
X
1
2
3
4