參數(shù)資料
型號: ZL50418GKC
廠商: Zarlink Semiconductor Inc.
英文描述: Managed 16-Port 10/100 M + 2-Port 1 G Ethernet Switch
中文描述: 管理16端口10/100平方米端口1個G以太網(wǎng)交換機
文件頁數(shù): 89/163頁
文件大小: 2122K
代理商: ZL50418GKC
ZL50418
Data Sheet
89
Zarlink Semiconductor Inc.
14.9.15 PR100 – Port Reservation for 10/100 ports
I
2
C Address h0B8, CPU Address 50E
Accessed by CPU, serial interface and I
2
C (R/W)
14.9.16 PRG – Port Reservation for Giga ports
I
2
C Address h0B9, CPU Address 50F
Accessed by CPU, serial interface and I
2
C (R/W)
Bit [4:0]:
In multiples of two frames (granularity). Used for triggering MC flow control
when destination port’s multicast best effort queue reaches MCC
threshold.(Default 0x10)
Bit [7:5]:
Flow control reaction period (Default 2) Granularity 4 uSec.
7
4
3
0
Buffer low threshold
SP Buffer reservation
Bit [3:0]:
Per source port buffer reservation.
Define the space in the FDB reserved for each 10/100 port and CPU.
Expressed in multiples of 4 packets. For each packet 1536 bytes are
reserved in the memory.
Bits [7:4]:
Expressed in multiples of 4 packets. Threshold for dropping all best effort
frames when destination port best efforts queues reaches UCC threshold,
shared pool is all used and source port reservation is at or below the
PR100[7:4] level. Also the threshold for initiating UC flow control.
Default:
- h36 for 16+2 configuration with memory 2 MB/bank;
- h24 for 16+2 configuration with 1 MB/bank;
7
4
3
0
Buffer low threshold
SP buffer reservation
Bit [3:0]:
Per source port buffer reservation.
Define the space in the FDB reserved for each Gigabit port. Expressed in
multiples of 16 packets. For each packet 1536 bytes are reserved in the
memory.
Bits [7:4]:
Expressed in multiples of 16 packets. Threshold for dropping all best effort
frames when destination port best effort queues reach UCC threshold,
shared pool is all used and source port reservation is at or below the
PRG[7:4] level. Also the threshold for initiating UC flow control.
Default:
- H58 for memory 2 MB/bank;
- H35 for 1 MB/bank;
相關(guān)PDF資料
PDF描述
ZL60101 12 x 2.7 Gbps Parallel Fiber Optic Link Transmitter and Receiver
ZL60101MJD 12 x 2.7 Gbps Parallel Fiber Optic Link Transmitter and Receiver
ZL60102 12 x 2.7 Gbps Parallel Fiber Optic Link Transmitter and Receiver
ZL60102MJD 12 x 2.7 Gbps Parallel Fiber Optic Link Transmitter and Receiver
ZL60212 880 nm High-Performance Single-chip DUPLEX
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL51B 制造商:YEASHIN 制造商全稱:YEASHIN 功能描述:500 mW DO-35 Hermetically Sealed Glass Zener Voltage Regulators
ZL56B 制造商:YEASHIN 制造商全稱:YEASHIN 功能描述:500 mW DO-35 Hermetically Sealed Glass Zener Voltage Regulators
ZL5V1B 制造商:YEASHIN 制造商全稱:YEASHIN 功能描述:500 mW DO-35 Hermetically Sealed Glass Zener Voltage Regulators
ZL5V6B 制造商:YEASHIN 制造商全稱:YEASHIN 功能描述:500 mW DO-35 Hermetically Sealed Glass Zener Voltage Regulators
ZL60001 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:High speed 2.5 Gbps 850 nm VCSEL