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參數(shù)資料
| 型號： | ZL30109QDG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | DS1/E1 System Synchronizer with |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 13/37頁 |
| 文件大?。?/td> | 751K |
| 代理商： | ZL30109QDG1 |
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ZL30109
Data Sheet
13
Zarlink Semiconductor Inc.
Figure 6 - E1 Mode Out-of-Range Limits (OOR_SEL=1)
3.3 Time Interval Error (TIE) Corrector Circuit
The TIE corrector circuit eliminates phase transients on the output clock that may occur during reference switching
or the recovery from Holdover mode to Normal mode.
On recovery from Holdover mode (dependent on the HMS pin) or when switching to another reference input, the
TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of the
selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual
reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL
minimizes the phase transient it experiences when it switches to another reference input or recovers from Holdover
mode.
The delay value can be reset by setting the TIE corrector circuit Clear pin (TIE_CLR) low for at least 15 ns. This
results in a phase alignment between the input reference signal and the output clocks and frame pulses as shown
in Figure 16 and Figure 17. The speed of the phase alignment correction is limited to 61
μ
s/s when BW_SEL=0.
Convergence is always in the direction of least phase travel. In general the TIE correction should not be exercised
when Holdover mode is entered for short time periods. TIE_CLR can be kept low continuously; in that case the
output clocks will always be aligned with the selected input reference. This is illustrated in Figure 7.
0 ppm
+50 ppm
-50 ppm
0
80
130
100
C20
C20
50
50
-50
-150
-150
-100
0
-200
-50
50
150
200
Frequency
Offset [ppm]
Out of Range
Out of Range
Out of Range
In Range
In Range
In Range
0
0
C20
100
-100
-130
180
150
-50
-80
-180
C20: 20 MHz master clock on OSCi
C20 Clock Accuracy
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| ZL30109 | DS1/E1 System Synchronizer with 19.44 MHz Output |
| ZL30109QDG | DS1/E1 System Synchronizer with 19.44 MHz Output |
| ZL30110 | Telecom Rate Conversion DPLL |
| ZL30110LDE | Telecom Rate Conversion DPLL |
| ZL30110LDE1 | Telecom Rate Conversion DPLL |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30110 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Telecom Rate Conversion DPLL |
| ZL30110LDE | 制造商:Microsemi Corporation 功能描述: 制造商:Microsemi Corporation 功能描述:PLL FREQ SYNTHESIZER TRIPLE 32QFN - Rail/Tube |
| ZL30110LDE1 | 制造商:Microsemi Corporation 功能描述: |
| ZL30110LDF1 | 制造商:Microsemi Corporation 功能描述:PB FREE TELECOM RATE CONVERSION DPLL - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE TELECOM RATE CONVERSION DPLL - Tape and Reel |
| ZL30110LDG1 | 制造商:Microsemi Corporation 功能描述:PB FREE TELECOM RATE CONVERSION DPLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DPLL RATE CONVERSION 32QFN 制造商:Microsemi Corporation 功能描述:IC DPLL RATE CONVERSION 32QFN |
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