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參數(shù)資料
| 型號： | ZL30110LDE |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Telecom Rate Conversion DPLL |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, MO-220, QFN-32 |
| 文件頁數(shù)： | 1/21頁 |
| 文件大小： | 270K |
| 代理商： | ZL30110LDE |
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or
16.384 MHz
Provides a range of output clocks:
65.536 MHz TDM clock locked to the input
reference
General purpose 25 MHz fan-out to 6 outputs
locked to the external crystal or oscillator
General purpose 125 MHz and 66 MHz or
100 MHz locked to the external crystal or
oscillator
Provides DPLL lock and reference fail indication
Automatic free run mode on reference fail
DPLL bandwidth of 922 Hz for all rates of input
reference and 58 Hz for an 8 kHz input reference
Less than 5 psec
rms
on 25 MHz outputs, and less
than 0.6 ns
pp
intrinsic jitter on the all other outputs
Minimal input to output and output to output skew
25 MHz external master clock source: clock
oscillator or crystal
Simple hardware control interface
Applications
Clock rate conversion PLL for Telecommunication
Equipment
Small/Medium Enterprise Router / Gateway
Broadband access (xPON/xDSL) CPE gateway
Description
The ZL30110 clock rate conversion digital phase-
locked loop (DPLL) provides accurate and reliable
frequency conversion.
The ZL30110 generates a range of clocks that are
either locked to the input reference or locked to the
external crystal or oscillator.
In the locked mode, the reference input is continuously
monitored for a failure condition. In the event of a
failure, the DPLL continues to provide a stable free
running clock ensuring system reliability.
November 2006
Ordering Information
ZL30110LDE
ZL30110LDE1
32 Pin QFN
32 Pin QFN*
*Pb Free Matte Tin
Tubes Bake & Dry Pack
Tubes Bake & Dry Pack
-40
°
C to +85
°
C
ZL30110
Telecom Rate Conversion DPLL
Data Sheet
Figure 1 - Functional Block Diagram
RST
OSCo
OSCi
REF
LOCK
APLL
C65o
REF_FAIL
C100/66o
DPLL
6 X C25o
APLL
C125o
OUT_SEL
State Machine
Reference
Monitor
Master
Clock
Frequency
Synthesizer
Select MUX
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30110LDE1 | Telecom Rate Conversion DPLL |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30110LDE1 | 制造商:Microsemi Corporation 功能描述: |
| ZL30110LDF1 | 制造商:Microsemi Corporation 功能描述:PB FREE TELECOM RATE CONVERSION DPLL - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE TELECOM RATE CONVERSION DPLL - Tape and Reel |
| ZL30110LDG1 | 制造商:Microsemi Corporation 功能描述:PB FREE TELECOM RATE CONVERSION DPLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DPLL RATE CONVERSION 32QFN 制造商:Microsemi Corporation 功能描述:IC DPLL RATE CONVERSION 32QFN |
| ZL30111 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:POTS Line Card PLL |
| ZL301116GGG2ENG1 | 制造商:Microsemi Corporation 功能描述: |
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