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參數(shù)資料
| 型號(hào)： | ZL30110LDE |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Telecom Rate Conversion DPLL |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, MO-220, QFN-32 |
| 文件頁數(shù)： | 11/21頁 |
| 文件大小： | 270K |
| 代理商： | ZL30110LDE |
ZL30110
Data Sheet
11
Zarlink Semiconductor Inc.
4.0 Measures of Performance
The following are some PLL performance indicators and their corresponding definitions.
4.1 Jitter
Timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander
is defined as the low-frequency variation of the clock edges from their ideal positions in time. High and low
frequency variation imply phase oscillation frequencies relative to some demarcation frequency. (Often 10 Hz or
20 Hz for DS1 or E1, higher for SONET/SDH clocks.) Jitter parameters given in this data sheet are total timing jitter
numbers, not cycle-to-cycle jitter.
4.2 Jitter Generation (Intrinsic Jitter)
Jitter generation is the measure of the jitter produced by the PLL and is measured at its output. It is measured by
applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Jitter is usually
measured with various band limiting filters depending on the applicable standards.
4.3 Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
4.4 Lock Time
This is the time it takes the PLL to frequency lock to the input signal. Phase lock occurs when the input signal and
output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter).
Lock time is affected by many factors which include:
initial input to output phase difference
initial input to output frequency difference
PLL loop filter bandwidth
The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output
to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and
frequency.
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PDF描述 |
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| ZL30110LDE1 | Telecom Rate Conversion DPLL |
| ZL30111 | POTS Line Card PLL |
| ZL30111QDG | POTS Line Card PLL |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30110LDE1 | 制造商:Microsemi Corporation 功能描述: |
| ZL30110LDF1 | 制造商:Microsemi Corporation 功能描述:PB FREE TELECOM RATE CONVERSION DPLL - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE TELECOM RATE CONVERSION DPLL - Tape and Reel |
| ZL30110LDG1 | 制造商:Microsemi Corporation 功能描述:PB FREE TELECOM RATE CONVERSION DPLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DPLL RATE CONVERSION 32QFN 制造商:Microsemi Corporation 功能描述:IC DPLL RATE CONVERSION 32QFN |
| ZL30111 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:POTS Line Card PLL |
| ZL301116GGG2ENG1 | 制造商:Microsemi Corporation 功能描述: |
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