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參數(shù)資料
| 型號： | ZL30110LDE |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Telecom Rate Conversion DPLL |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, MO-220, QFN-32 |
| 文件頁數(shù)： | 18/21頁 |
| 文件大?。?/td> | 270K |
| 代理商： | ZL30110LDE |
ZL30110
Data Sheet
18
Zarlink Semiconductor Inc.
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Figure 9 - Asynchronous Clocks Input to Output Timing
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
** Buffered OSCi clock input, characterization data did not account for input clock duty cycle nor rise/fall time degradation.
6.2 Performance Characteristics
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
AC Electrical Characteristics* - Input to output timing for Asynchronous clocks (see Figure 9).
Characteristics
Symbol
Min.
Max.
Units
Notes
1
25 MHz master clock input to C25a/b/c/d/e/fo
delay
t
M_C25D
3
14
ns
AC Electrical Characteristics* - Output timing for Asynchronous clocks (see Figure 9).
Characteristics
Symbol
Min.
Max.
Units
Notes
1
C25a/b/c/d/e/fo pulse width low
**
t
C25L
t
C125L
t
C100L
t
C66L
18
22
ns
30 pF output load
2
C125o pulse width low
3.2
4.6
ns
25 pF output load
3
C100o pulse width low
4.1
5.6
ns
30 pF output load
4
C66o pulse width low
6.8
8.0
ns
30 pF output load
Performance Characteristics* - Functional
Characteristics
Min.
Typ.
Max.
Units
Notes
1
DPLL capture range
-130
+130
ppm
The 25 MHz Master Clock
oscillator set at 0.ppm
Lock Time
2
DPLL 58 Hz Filter
1
s
input reference = 8 kHz,
±
100 ppm frequency
offset
3
DPLL 922 Hz Filter
1
s
input reference
≠
8 kHz,
±
100 ppm frequency
offset
4
APLL 450 kHz Filter
150
μ
s
Master Clock
t
M_C25D
Asynchronous
Output Clocks
25MHz
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| ZL30110LDE1 | 制造商:Microsemi Corporation 功能描述: |
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