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參數(shù)資料
| 型號： | ZL30109QDG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | DS1/E1 System Synchronizer with |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 1/37頁 |
| 文件大小： | 751K |
| 代理商： | ZL30109QDG1 |
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1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Supports Telcordia GR-1244-CORE Stratum 4 and
Stratum 4E
Supports ITU-T G.823 and G.824 for 2048 kbit/s and
1544 kbit/s interfaces
Supports ANSI T1.403 and ETSI ETS 300 011 for
ISDN primary rate interfaces
Simple hardware control interface
Accepts two input references and synchronizes to
any combination of 2 kHz, 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
inputs
Provides a range of clock outputs: 1.544 MHz,
2.048 MHz, 16.384 MHz, 19.44 MHz and either
4.096 MHz and 8.192 MHz or 32.768 MHz and
65.536 MHz
Hitless reference switching between any
combination of valid input reference frequencies
Provides 5 styles of 8 kHz framing pulses and a
2 kHz multi-frame pulse
Holdover frequency accuracy of 1.5 x 10
-7
Lock, Holdover and selectable Out of Range
indication
Selectable loop filter bandwidth of 1.8 Hz or 922 Hz
Less than 24 ps
rms
intrinsic jitter on the
19.44 MHz output clock, compliant with OC-3 and
STM-1 jitter specifications
Less than 0.6 ns
pp
intrinsic jitter on all output
clocks
External master clock source: clock oscillator or
crystal
Applications
Synchronization and timing control for DSLAM,
Gateway and PBX systems that require Stratum
4/4E timing
Line Card synchronization for SDH/PDH
applications
Clock and frame pulse source for ST-BUS, GCI
and other time division multiplex (TDM) buses
November 2005
ZL30109
DS1/E1 System Synchronizer with
19.44 MHz Output
Data Sheet
Figure 1 - Functional Block Diagram
Reference
Monitor
Mode
Control
Virtual
Reference
IEEE
1149.1a
Feedback
TIE
Corrector
Enable
State Machine
Frequency
Select
MUX
TIE
Corrector
Circuit
MODE_SEL1:0
TCK
REF1
RST
REF_SEL
TIE_CLR
OSCo
OSCi
Master Clock
TDO
REF0
TDI
TMS
TRST
HOLDOVER
BW_SEL
HMS
LOCK
REF_FAIL0
REF_FAIL1
DPLL
OUT_SEL
MUX
OOR_SEL
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
E1
Synthesizer
DS1
Synthesizer
SONET/SDH
Synthesizer
C1.5o
C19o
F2ko
Ordering Information
ZL30109QDG
ZL30109QDG1 64 pin TQFP* Trays, Bake & Drypack
64 Pin TQFP
Trays, Bake & Drypack
*Pb Free Matte Tin
-40
°
C to +85
°
C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30109 | DS1/E1 System Synchronizer with 19.44 MHz Output |
| ZL30109QDG | DS1/E1 System Synchronizer with 19.44 MHz Output |
| ZL30110 | Telecom Rate Conversion DPLL |
| ZL30110LDE | Telecom Rate Conversion DPLL |
| ZL30110LDE1 | Telecom Rate Conversion DPLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30110 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Telecom Rate Conversion DPLL |
| ZL30110LDE | 制造商:Microsemi Corporation 功能描述: 制造商:Microsemi Corporation 功能描述:PLL FREQ SYNTHESIZER TRIPLE 32QFN - Rail/Tube |
| ZL30110LDE1 | 制造商:Microsemi Corporation 功能描述: |
| ZL30110LDF1 | 制造商:Microsemi Corporation 功能描述:PB FREE TELECOM RATE CONVERSION DPLL - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE TELECOM RATE CONVERSION DPLL - Tape and Reel |
| ZL30110LDG1 | 制造商:Microsemi Corporation 功能描述:PB FREE TELECOM RATE CONVERSION DPLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DPLL RATE CONVERSION 32QFN 制造商:Microsemi Corporation 功能描述:IC DPLL RATE CONVERSION 32QFN |
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