參數(shù)資料
型號： ZL30109
廠商： Zarlink Semiconductor Inc.
英文描述： DS1/E1 System Synchronizer with 19.44 MHz Output
中文描述： 的DS1/E1系統(tǒng)同步與19.44 MHz輸出
文件頁數(shù)： 21/36頁
文件大?。?/td> 474K
代理商： ZL30109
ZL30109
Data Sheet
21
Zarlink Semiconductor Inc.
4.5 Frequency Accuracy
Frequency accuracy is defined as the absolute accuracy of an output clock signal when it is not locked to an
external reference, but is operating in a free running mode.
4.6 Holdover Accuracy
Holdover accuracy is defined as the absolute accuracy of an output clock signal, when it is not locked to an external
reference signal, but is operating using storage techniques. For the ZL30109, the storage value is determined while
the device is in Normal Mode and locked to an external reference signal.
4.7
Pull-in
Range
Also referred to as capture range. This is the input frequency range over which the PLL must be able to pull into
synchronization.
4.8 Lock Range
This is the input frequency range over which the synchronizer must be able to maintain synchronization.
4.9 Phase Slope
Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect
to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is
nominally equal to the value of the final output signal or final input signal. Another way of specifying the phase slope
is as the fractional change per time unit. For example; a phase slope of 61
μ
s/s can also be specified as 61 ppm.
4.10 Time Interval Error (TIE)
TIE is the time delay between a given timing signal and an ideal timing signal.
4.11 Maximum Time Interval Error (MTIE)
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a
particular observation period.
4.12 Phase Continuity
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a
particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency.
Phase continuity applies to the output of the PLL after a signal disturbance due to a reference switch or a mode
change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to
a steady state.
4.13 Lock Time
This is the time it takes the PLL to frequency lock to the input signal. Phase lock occurs when the input signal and
output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter).
Lock time is affected by many factors which include:
initial input to output phase difference
initial input to output frequency difference
PLL loop filter bandwidth
PLL phase slope limiter
in-lock phase distance
相關PDF資料
PDF描述
ZL30109QDG DS1/E1 System Synchronizer with 19.44 MHz Output
ZL30110 Telecom Rate Conversion DPLL
ZL30110LDE Telecom Rate Conversion DPLL
ZL30110LDE1 Telecom Rate Conversion DPLL
ZL30111 POTS Line Card PLL
相關代理商/技術參數(shù)
參數(shù)描述
ZL30109_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:DS1/E1 System Synchronizer with
ZL30109QDG 制造商:Microsemi Corporation 功能描述:
ZL30109QDG1 制造商:Microsemi Corporation 功能描述:DS1/E1 System Synchronizer 64-Pin TQFP 制造商:Microsemi Corporation 功能描述:DS1/E1 SYS. SYNCH WITH 19.44MHZ 制造商:Microsemi Corporation 功能描述:DS1/E1 SYS SYNCHRONIZER 64TQFP - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SYNCHRONIZER DPLL 64TQFP 制造商:Microsemi Corporation 功能描述:IC SYNCHRONIZER DPLL 64TQFP
ZL30110 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Telecom Rate Conversion DPLL
ZL30110LDE 制造商:Microsemi Corporation 功能描述: 制造商:Microsemi Corporation 功能描述:PLL FREQ SYNTHESIZER TRIPLE 32QFN - Rail/Tube
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