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參數(shù)資料
| 型號： | ZL30109 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | DS1/E1 System Synchronizer with 19.44 MHz Output |
| 中文描述： | 的DS1/E1系統(tǒng)同步與19.44 MHz輸出 |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 474K |
| 代理商： | ZL30109 |
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ZL30109
Data Sheet
16
Zarlink Semiconductor Inc.
In Normal mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Holdover mode, the DCO is free running at a frequency equal to the frequency that the DCO was generating in
Normal mode. The frequency in Holdover mode is calculated from frequency samples stored 26 ms to 52 ms before
the ZL30109 entered Holdover mode. This ensures that the coarse frequency monitor and the single cycle monitor
have time to disqualify a bad reference before it corrupts the holdover frequency.
In Freerun mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source.
Lock Indicator
- the lock detector monitors if the output value of the phase detector is within the
phase-lock-window for a certain time. The selected phase-lock-window guarantees the stable operation of the
LOCK pin with maximum network jitter and wander on the reference input. If the DPLL is locked and then goes into
Holdover mode (auto or manual), the LOCK pin will initially stay high for 1 s. If at that point the DPLL is still in
holdover mode, the LOCK pin will go low; subsequently the LOCK pin will not return high for at least the full
lock-time duration. In Freerun mode the LOCK pin will go low immediately.
2.5 Frequency Synthesizers
The output of the DCO is used by the frequency synthesizers to generate the C1.5o, C2o, C4o, C8o, C16o, C19o,
C32o and C65o clocks and the F4o, F8o, F16o, F32o, F65o and F2ko frame pulses which are synchronized to the
selected reference input (REF0 or REF1). The frequency synthesizers use digital techniques to generate output
clocks and advanced noise shaping techniques to minimize the output jitter. The clock and frame pulse outputs
have limited driving capability and should be buffered when driving high capacitance loads.
2.6 State Machine
As shown in Figure 1, the control state machine controls the TIE Corrector Circuit and the DPLL. The control of the
ZL30109 is based on the inputs MODE_SEL1:0, REF_SEL and HMS.
2.7 Master Clock
The ZL30109 can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
3.0 Control and Modes of Operation
3.1 Out of Range Selection
The frequency out of range limits for the precise frequency monitoring in the reference monitors are selected by the
OOR_SEL pin, see Table 1.
OOR_SEL
Application
Applicable Standard
Out Of Range Limits
0
DS1
ANSI T1.403
Telcordia GR-1244-CORE Stratum 4/4E
64 - 83 ppm
1
E1
ITU-T G.703
ETSI ETS 300 011
100 - 130 ppm
Table 1 - Out of Range Limits Selection
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