參數(shù)資料
型號: ZL30109
廠商: Zarlink Semiconductor Inc.
英文描述: DS1/E1 System Synchronizer with 19.44 MHz Output
中文描述: 的DS1/E1系統(tǒng)同步與19.44 MHz輸出
文件頁數(shù): 19/36頁
文件大?。?/td> 474K
代理商: ZL30109
ZL30109
Data Sheet
19
Zarlink Semiconductor Inc.
Figure 10 - Mode Switching in Normal Mode
3.5 Reference Selection
The active reference input (REF0, REF1) is selected by the REF_SEL pin as shown in Table 5. If the logic value of
the REF_SEL pin is changed when the DPLL is in Normal mode, the ZL30109 will perform a hitless reference
switch.
When the REF_SEL inputs are used to force a change from the currently selected reference to another reference,
the action of the LOCK output will depend on the relative frequency and phase offset of the old and new references.
Where the new reference has enough frequency offset and/or TIE-corrected phase offset to force the output
outside the phase-lock-window, the LOCK output will de-assert, the lock-qualify timer is reset, and LOCK will stay
de-asserted for the full lock-time duration. Where the new reference is close enough in frequency and
TIE-corrected phase for the output to stay within the phase-lock-window, the LOCK output will remain asserted
through the reference-switch process.
REF_SEL
(input pin)
Input Reference Selected
0
REF0
1
REF1
Table 5 - Reference Selection
REF_DIS=1: Current selected reference disrupted (see Figure 3). This is an internal signal.
REF_CH= 1: Reference change, a change in the REF_SEL pin. This is an internal signal.
TIE Correction
(HOLDOVER=1)
Holdover
(HOLDOVER=1)
REF_DIS=0
REF_CH=1
REF_DIS=0 and
REF_CH=0 and
HMS=0
REF_DIS=1
(REF_DIS=0 and HMS=1) or
REF_CH=1
REF_DIS=1
RST
Normal
(HOLDOVER=0)
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