- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373783 > ZL30102 (Zarlink Semiconductor Inc.) T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 PDF資料下載
參數(shù)資料
| 型號： | ZL30102 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| 中文描述： | T1/E1的地層4/4E冗余系統(tǒng)時(shí)鐘同步的的DS1/E1和H.110 |
| 文件頁數(shù)： | 23/50頁 |
| 文件大?。?/td> | 481K |
| 代理商： | ZL30102 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁
ZL30102
Data Sheet
23
Zarlink Semiconductor Inc.
4.4.3 Normal Mode
Normal mode is typically used when a system clock source, synchronized to the network is required. In Normal
mode, the ZL30102 provides timing (C1.5o, C2o, C4o, C8o, C16o, C19o, C32 and C65o) and frame
synchronization (F2ko, F4o, F8o, F16o, F32o and F65o) signals, which are synchronized to one of three reference
inputs (REF0, REF1 or REF2). The input reference signal may have a nominal frequency of 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz or 16.384 MHz. The frequency of the reference inputs are automatically detected by the
reference monitors.
When the ZL30102 comes out of RESET while Normal mode is selected by its MODE_SEL pins then it will initially
go into Holdover mode and generate clocks with the accuracy of its freerunning local oscillator (see Figure 11). If
the ZL30102 determines that its selected reference is disrupted (see Figure 3), it will remain in Holdover until the
selected reference is no longer disrupted or the external controller selects another reference that is not disrupted. If
the ZL30102 determines that its selected reference is not disrupted (see Figure 3) then the state machine will cause
the DPLL to recover from Holdover via one of two paths depending on the logic level at the HMS pin. If HMS=0 then
the ZL30102 will transition directly to Normal mode and it will align its output signals with its selected input
reference (see Figure 9). If HMS=1 then the ZL30102 will transition to Normal mode via the TIE correction state and
the phase difference between the output signals and the selected input reference will be maintained.
When the ZL30102 is operating in Normal mode, if it determines that its selected reference is disrupted (Figure 3)
then its state machine will cause it to automatically go to Holdover mode. When the ZL30102 determines that its
selected reference is not disrupted then the state machine will cause the DPLL to recover from Holdover via one of
two paths depending on the logic level at the HMS pin (see Figure 11). If HMS=0 then the ZL30102 will transition
directly to Normal mode and it will align its output signals with its input reference (see Figure 9). If HMS=1 then the
ZL30102 will transition to Normal mode via the TIE correction state and the phase difference between the output
signals and the input reference will be maintained.
If the reference selection changes because the value of the REF_SEL1:0 pins changes or because the reference
selection state machine selected a different reference input, the ZL30102 goes into Holdover mode and returns to
Normal mode through the TIE correction state regardless of the logic value on HMS pin.
ZL30102 provides a fast lock pin (FASTLOCK), which, when set high enables the PLL to lock to an incoming
reference within approximately 1 s.
Figure 11 - Mode Switching in Normal Mode
REF_DIS=1: Current selected reference disrupted (see Figure 3). REF_DIS is an internal signal.
REF_CH= 1: Reference change, a transition in the reference selection (see Figure 13) or a change in the
REF_SEL pins. REF_CH is an internal signal.
TIE Correction
(HOLDOVER=1)
Holdover
(HOLDOVER=1)
REF_DIS=0
REF_CH=1
REF_DIS=0 and
REF_CH=0 and
HMS=0
REF_DIS=1
(REF_DIS=0 and HMS=1) or
REF_CH=1
REF_DIS=1
RST
Normal
(HOLDOVER=0)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30102QDG | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| ZL30105QDG1 | T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110 |
| ZL30105 | Power Clamp On Multimeter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Approval Categories:CAT III 600V; Calibrated:No; Current Measuring Range:0-400.0A; Current Setting AC:400A RoHS Compliant: NA |
| ZL30105QDG | Digital Clamp-On Meter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Calibrated:No; Current Setting AC:1000A; Resistance Measuring Range:400 Ohm to 10 MOhm; Voltage Measuring Range AC:600V RoHS Compliant: NA |
| ZL30106QDG1 | SONET/SDH/PDH Network Interface DPLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30102_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| ZL30102QDG | 制造商:Zarlink Semiconductor Inc 功能描述:PLL CLOCK SYNTHESIZER SGL 64TQFP - Trays |
| ZL30102QDG1 | 制造商:Microsemi Corporation 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays |
| ZL30105 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110 |
| ZL30105_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。