參數(shù)資料
型號： ZL30102
廠商： Zarlink Semiconductor Inc.
英文描述： T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
中文描述： T1/E1的地層4/4E冗余系統(tǒng)時鐘同步的的DS1/E1和H.110
文件頁數(shù)： 21/50頁
文件大?。?/td> 481K
代理商： ZL30102
ZL30102
Data Sheet
21
Zarlink Semiconductor Inc.
4.0 Control and Modes of Operation
4.1 Out of Range Selection
The out of range limits for the Precise Frequency Monitor in the 3 reference monitor blocks are selected through the
OOR_SEL pin, see Table 1.
4.2 Loop Filter and Limiter Selection
The loop filter and limiter settings are selected through the SEC_MSTR pin, see Table 2. The maximum loop filter
bandwidth is also dependent on the frequency of the currently selected reference (REF0/1/2).
4.3 Output Clock and Frame Pulse Selection
The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which
are synchronized to one of three reference inputs (REF0, REF1 or REF2). These signals are available in two
groups controlled by the OUT_SEL pin, see Table 3.
4.4 Modes of Operation
The ZL30102 has three possible manual modes of operation; Normal, Holdover and Freerun. These modes are
selected with mode select pins MODE_SEL1 and MODE_SEL0 as is shown in Table 4. Transitioning from one
mode to the other is controlled by an external controller. The ZL30102 can be configured to automatically select a
valid input reference under control of its internal state machine by setting MODE_SEL1:0 = 11. In this mode of
operation, a state machine controls selection of references (REF0 or REF1) used for synchronization.
OOR_SEL
Application
Applicable Standard
Out Of Range Limits
0
DS1
ANSI T1.403
Telcordia GR-1244-CORE Stratum 4/4E
64 - 83 ppm
1
E1
ITU-T G.703
ETSI ETS 300 011
100 - 130 ppm
Table 1 - Out of Range Limits Selection
SEC_MSTR
Detected REF Frequency
Loop Filter Bandwidth
Phase Slope Limiting
0
any
1.8 Hz
61
μ
/s
1
8 kHz
58 Hz
9.5 ms /s
1.544 MHz, 2.048 MHz,
8.192 MHz, 16.384 MHz
922 Hz
9.5 ms /s
Table 2 - Loop Filter and Limiter Settings
OUT_SEL
Generated Clocks
Generated Frame Pulses
0
C2o, C4o, C8o, C16o
F4o, F8o, F16o
1
C2o, C16o, C32, C65o
F16o, F32o, F65o
Table 3 - Clock and Frame Pulse Selection with OUT_SEL Pin
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