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參數(shù)資料
| 型號： | ZL30100QDG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | T1/E1 System Synchronizer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 9/36頁 |
| 文件大小： | 346K |
| 代理商： | ZL30100QDG1 |
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ZL30100
Data Sheet
9
Zarlink Semiconductor Inc.
19
RST
Reset (Input).
A logic low at this input resets the device. On power up, the RST pin
must be held low for a minimum of 300 ns after the power supply pins have reached
the minimum supply voltage. When the RST pin goes high, the device will transition
into a Reset state for 3 ms. In the Reset state all clock and frame pulse outputs will be
forced into high impedance.
20
OSCo
Oscillator Master Clock (Output).
For crystal operation, a 20 MHz crystal is connected
from this pin to OSCi. This output is not suitable for driving other devices. For clock
oscillator operation, this pin must be left unconnected.
21
OSCi
Oscillator Master Clock (Input).
For crystal operation, a 20 MHz crystal is connected
from this pin to OSCo. For clock oscillator operation, this pin must be connected to a
clock source.
22
IC
Internal Connection.
Leave unconnected.
23
GND
Ground.
0 V.
24
NC
No internal bonding Connection.
Leave unconnected.
25
V
DD
Positive Supply Voltage.
+3.3 V
DC
nominal.
Output Selection (Input).
This input selects the signals on the combined output clock
and frame pulse pins, see Table 3 on page 18.
26
OUT_SEL
27
IC
Internal Connection.
Connect this pin to ground.
28
IC
Internal Connection.
Connect this pin to ground.
29
AV
DD
NC
Positive Analog Supply Voltage.
+3.3 V
DC
nominal.
No internal bonding Connection.
Leave unconnected.
30
31
NC
No internal bonding Connection.
Leave unconnected.
32
C1.5o
Clock 1.544 MHz (Output).
This output is used in DS1 applications.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
33
AGND
Analog Ground.
0 V
34
AGND
Analog Ground.
0 V
35
AV
CORE
AV
DD
AV
DD
NC
Positive Analog Supply Voltage.
+1.8 V
DC
nominal.
Positive Analog Supply Voltage.
+3.3 V
DC
nominal.
Positive Analog Supply Voltage.
+3.3 V
DC
nominal.
No internal bonding Connection.
Leave unconnected.
36
37
38
39
NC
No internal bonding Connection.
Leave unconnected.
40
AGND
Analog Ground.
0 V
41
AGND
Analog Ground.
0 V
42
C4/C65o
Clock 4.096 MHz or 65.536 MHz (Output).
This output is used for ST-BUS operation at
2.048 Mbps, 4.096 Mbps or 65.536 MHz (ST-BUS 65.536 Mbps). The output frequency is
selected via the OUT_SEL pin.
Pin Description (continued)
Pin #
Name
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30100 | T1/E1 System Synchronizer |
| ZL30100QDC | T1/E1 System Synchronizer |
| ZL30101QDG1 | T1/E1 Stratum 3 System Synchronizer |
| ZL30101 | T1/E1 Stratum 3 System Synchronizer |
| ZL30101QDC | T1/E1 Stratum 3 System Synchronizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30101 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 3 System Synchronizer |
| ZL30101_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 3 System Synchronizer |
| ZL30101QDC | 制造商:Microsemi Corporation 功能描述: |
| ZL30101QDG1 | 制造商:Microsemi Corporation 功能描述:SYS SYNCHRONIZER 64TQFP - Trays |
| ZL30102 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
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