參數(shù)資料
型號(hào)： ZL30100QDG1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： T1/E1 System Synchronizer
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64
文件頁(yè)數(shù)： 23/36頁(yè)
文件大?。?/td> 346K
代理商： ZL30100QDG1
ZL30100
Data Sheet
23
Zarlink Semiconductor Inc.
in-lock phase distance
The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output
to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and
frequency.
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. And better (smaller) phase slope performance (limiter) results in longer lock times.
6.0 Applications
This section contains ZL30100 application specific details for power supply decoupling, reset operation, clock and
crystal operation.
6.1 Power Supply Decoupling
Jitter levels on the ZL30100 output clocks may increase if the device is exposed to excessive noise on its power
pins. For optimal jitter performance, the ZL30100 device should be isolated from noise on power planes connected
to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note
ZLAN-178.
6.2 Master Clock
The ZL30100 can use either a clock or crystal as the master timing source. Zarlink application note ZLAN-68 lists a
number of applicable oscillators and crystals that can be used with the ZL30100.
6.2.1 Clock Oscillator
When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency,
frequency change over temperature, phase noise, output rise and fall times, output levels and duty cycle.
The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30100, and the OSCo
output should be left open as shown in Figure 12.
1
Frequency
20 MHz
2
Tolerance
as required
3
Rise & fall time
< 10 ns
4
Duty cycle
40% to 60%
Table 6 - Typical Clock Oscillator Specification
相關(guān)PDF資料
PDF描述
ZL30100 T1/E1 System Synchronizer
ZL30100QDC T1/E1 System Synchronizer
ZL30101QDG1 T1/E1 Stratum 3 System Synchronizer
ZL30101 T1/E1 Stratum 3 System Synchronizer
ZL30101QDC T1/E1 Stratum 3 System Synchronizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL30101 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 3 System Synchronizer
ZL30101_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 3 System Synchronizer
ZL30101QDC 制造商:Microsemi Corporation 功能描述:
ZL30101QDG1 制造商:Microsemi Corporation 功能描述:SYS SYNCHRONIZER 64TQFP - Trays
ZL30102 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
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