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參數(shù)資料
| 型號(hào)： | ZL30101QDG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | T1/E1 Stratum 3 System Synchronizer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64 |
| 文件頁(yè)數(shù)： | 1/35頁(yè) |
| 文件大小： | 328K |
| 代理商： | ZL30101QDG1 |
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1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Supports Telcordia GR-1244-CORE Stratum 3
Supports G.823 and G.824 for 2048 kbit/s and
1544 kbit/s interfaces
Supports ANSI T1.403 and ETSI ETS 300 011 for
ISDN primary rate interfaces
Simple hardware control interface
Accepts two input references and synchronizes to
any combination of 8 kHz, 1.544 MHz, 2.048 MHz,
8.192 MHz or 16.384 MHz inputs
Provides a range of clock outputs: 1.544 MHz,
2.048 MHz, 16.384 MHz and either 4.096 MHz &
8.192 MHz or 32.768 MHz & 65.536 MHz
Hitless reference switching between any
combination of valid input reference frequencies
Provides 5 styles of 8 kHz framing pulses
Holdover frequency accuracy of 1 x 10
-8
Lock, Holdover and Out of Range indication
Selectable loop filter bandwidth of 1.8 Hz or 922 Hz
Less than 0.6 ns
pp
jitter on all output clocks
External master clock source: clock oscillator or
crystal
Applications
Synchronization and timing control for multi-trunk
DS1/E1 systems such as DSLAMs, gateways and
PBXs
Clock and frame pulse source for ST-BUS, GCI
and other time division multiplex (TDM) buses
February 2006
Ordering Information
ZL30101QDC
ZL30101QDG1 64 Pin TQFP* Trays, Bake & Drypack
*Pb Free Matte Tin
-40
°
C to +85
°
C
64 pin TQFP
Trays
ZL30101
T1/E1 Stratum 3 System Synchronizer
Data Sheet
Figure 1 - Functional Block Diagram
Reference
Monitor
Mode
Control
Virtual
Reference
IEEE
1149.1a
Feedback
TIE
Corrector
Enable
State Machine
Frequency
Select
MUX
TIE
Corrector
Circuit
MODE_SEL1:0
TCK
REF1
RST
REF_SEL
TIE_CLR
C1.5o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
OSCo
OSCi
Master Clock
TDO
REF0
TDI
TMS
TRST
HOLDOVER
HMS
LOCK
REF_FAIL0
REF_FAIL1
DPLL
OUT_SEL
C2o
E1
Synthesizer
DS1
Synthesizer
MUX
BW_SEL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30101 | T1/E1 Stratum 3 System Synchronizer |
| ZL30101QDC | T1/E1 Stratum 3 System Synchronizer |
| ZL30102QDG1 | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| ZL30102 | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| ZL30102QDG | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30102 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| ZL30102_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| ZL30102QDG | 制造商:Zarlink Semiconductor Inc 功能描述:PLL CLOCK SYNTHESIZER SGL 64TQFP - Trays |
| ZL30102QDG1 | 制造商:Microsemi Corporation 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays |
| ZL30105 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110 |
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