參數(shù)資料
型號(hào)： ZL30101QDG1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： T1/E1 Stratum 3 System Synchronizer
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64
文件頁(yè)數(shù)： 17/35頁(yè)
文件大小： 328K
代理商： ZL30101QDG1
ZL30101
Data Sheet
17
Zarlink Semiconductor Inc.
Digitally Controlled Oscillator (DCO)
- the DCO receives the limited and filtered signal from the loop filter, and
based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is
dependent on the state of the ZL30101.
In Normal mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Holdover mode, the DCO is free running at a frequency equal to the frequency that the DCO was generating in
Normal mode. The frequency in Holdover mode is calculated from frequency samples stored 26 ms to 52 ms before
the ZL30101 entered Holdover mode.
In Freerun mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source.
Lock Indicator
- the lock detector monitors if the output value of the phase detector is within the
phase-lock-window for a certain time. The selected phase-lock-window guarantees the stable operation of the
LOCK pin with maximum network jitter and wander on the reference input. If the DPLL is locked and then goes into
Holdover mode (auto or manual), the LOCK pin will initially stay high for 1 s. If at that point the DPLL is still in
holdover mode, the LOCK pin will go low; subsequently the LOCK pin will not return high for at least the full
lock-time duration. In Freerun mode the LOCK pin will go low immediately.
3.5 Frequency Synthesizers
The output of the DCO is used by the frequency synthesizers to generate the C1.5o, C2o, C4o, C8o, C16o, C32o
and C65o clocks and the F4o, F8o, F16o, F32o and F65o frame pulses which are synchronized to the selected
reference input (REF0 or REF1). The frequency synthesizers use digital techniques to generate output clocks and
advanced noise shaping techniques to minimize the output jitter. The clock and frame pulse outputs have limited
driving capability and should be buffered when driving high capacitance loads.
3.6 State Machine
As shown in Figure 1, the control state machine controls the TIE Corrector Circuit and the DPLL. The control of the
ZL30101 is based on the inputs MODE_SEL1:0, REF_SEL and HMS.
3.7 Master Clock
The ZL30101 can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL30102 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
ZL30102_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
ZL30102QDG 制造商:Zarlink Semiconductor Inc 功能描述:PLL CLOCK SYNTHESIZER SGL 64TQFP - Trays
ZL30102QDG1 制造商:Microsemi Corporation 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays
ZL30105 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110
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