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參數(shù)資料
| 型號： | ZL30101QDG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | T1/E1 Stratum 3 System Synchronizer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 14/35頁 |
| 文件大?。?/td> | 328K |
| 代理商： | ZL30101QDG1 |
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ZL30101
Data Sheet
14
Zarlink Semiconductor Inc.
Figure 6 - Timing Diagram of Hitless Reference Switching
The Hitless Mode Switching (HMS) pin enables phase hitless returns from Freerun and Holdover modes to Normal
mode in a single reference operation. A logic low at the HMS input disables the TIE corrector circuit updating the
delay value thereby forcing the output of the PLL to gradually move back to the original point before it went into
Holdover mode. (see Figure 7). This prevents accumulation of phase in network elements. A logic high (HMS=1)
enables the TIE corrector circuit to update its delay value thereby preventing a large output phase movement after
return to Normal mode. This causes accumulation of phase in network elements. In both cases the PLL’s output
can be aligned with the input reference by setting TIE_CLR low. Regardless of the HMS pin state, reference
switching in the ZL30101 is always hitless unless TIE_CLR is kept low continuously.
locked to REF1
REF0
Output
Clock
TIE_CLR = 1
TIE_CLR = 0
REF1
REF0
Output
Clock
REF1
locked to REF1
REF0
Output
Clock
REF1
REF0
Output
Clock
REF1
locked to REF0
locked to REF0
相關PDF資料 |
PDF描述 |
|---|---|
| ZL30101 | T1/E1 Stratum 3 System Synchronizer |
| ZL30101QDC | T1/E1 Stratum 3 System Synchronizer |
| ZL30102QDG1 | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| ZL30102 | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| ZL30102QDG | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30102 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| ZL30102_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| ZL30102QDG | 制造商:Zarlink Semiconductor Inc 功能描述:PLL CLOCK SYNTHESIZER SGL 64TQFP - Trays |
| ZL30102QDG1 | 制造商:Microsemi Corporation 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays |
| ZL30105 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110 |
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