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參數(shù)資料
| 型號： | ZL30100QDG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | T1/E1 System Synchronizer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 346K |
| 代理商： | ZL30100QDG1 |
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ZL30100
Data Sheet
16
Zarlink Semiconductor Inc.
-
13 ns is the maximum phase discontinuity in the transition from the Holdover mode to the Normal mode
when a new TIE corrector value is calculated.
HMS=0
: When the same ten Normal to Holdover to Normal mode changes occur and in each case Holdover mode
was entered for 2 seconds, then the overall MTIE would be 300 ns. As the delay value for the TIE corrector circuit is
not updated, there is no 13 ns measurement error at this point. The phase can still drift for 300 ns when the PLL is
in Holdover mode but when the PLL enters Normal mode again, the phase moves back to the original point so the
phase is not accumulated.
3.4 Digital Phase Lock Loop (DPLL)
The DPLL of the ZL30100 consists of a phase detector, a limiter, a loop filter, a digitally controlled oscillator (DCO)
and a lock indicator, as shown in Figure 9. The data path from the phase detector to the limiter is tapped and routed
to the lock indicator that provides a lock indication which is output at the LOCK pin.
Figure 9 - DPLL Block Diagram
Phase Detector
- the phase detector compares the virtual reference signal from the TIE corrector circuit with the
feedback signal and provides an error signal corresponding to the phase difference between the two. This error
signal is passed to the limiter circuit.
Limiter
- the limiter receives the error signal from the phase detector and ensures that the DPLL responds to all
input transient conditions with a maximum output phase slope of 61
μ
s/s or 9.5 ms/s, see Table 2.
Loop Filter
- the loop filter is similar to a first order low pass filter with a narrow or wide bandwidth suitable to
provide system synchronization or line card timing, see Table 2. The wide bandwidth can be used to closely track
the input reference in the presence of jitter or it can be temporarily enabled for fast locking to a new reference (1 s
lock time).
Digitally Controlled Oscillator (DCO)
- the DCO receives the limited and filtered signal from the loop filter, and
based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is
dependent on the state of the ZL30100.
State Select from
Control State Machine
Feedback signal from
Frequency Select MUX
DPLL Reference to
Frequency Synthesizer
Virtual Reference
from
TIE Corrector Circuit
Limiter
Loop Filter
Digitally
Controlled
Oscillator
Phase
Detector
Lock
indicator
LOCK
相關PDF資料 |
PDF描述 |
|---|---|
| ZL30100 | T1/E1 System Synchronizer |
| ZL30100QDC | T1/E1 System Synchronizer |
| ZL30101QDG1 | T1/E1 Stratum 3 System Synchronizer |
| ZL30101 | T1/E1 Stratum 3 System Synchronizer |
| ZL30101QDC | T1/E1 Stratum 3 System Synchronizer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30101 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 3 System Synchronizer |
| ZL30101_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 3 System Synchronizer |
| ZL30101QDC | 制造商:Microsemi Corporation 功能描述: |
| ZL30101QDG1 | 制造商:Microsemi Corporation 功能描述:SYS SYNCHRONIZER 64TQFP - Trays |
| ZL30102 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
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