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參數(shù)資料
| 型號： | ZL30100QDG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | T1/E1 System Synchronizer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 18/36頁 |
| 文件大小： | 346K |
| 代理商： | ZL30100QDG1 |
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ZL30100
Data Sheet
18
Zarlink Semiconductor Inc.
4.2 Loop Filter Selection
The loop filter settings can be selected through the BW_SEL pin, see Table 2.
4.3 Output Clock and Frame Pulse Selection
The output clock and frame pulses of the frequency synthesizers are available in two groups controlled by the
OUT_SEL input. Table 3 lists the supported combinations of output clocks and frame pulses.
4.4 Modes of Operation
The ZL30100 has three possible manual modes of operation; Normal, Holdover and Freerun. These modes are
selected with the mode select pins MODE_SEL1 and MODE_SEL0 as is shown in Table 4. Transitioning from one
mode to the other is controlled by an external controller.
4.4.1 Freerun Mode
Freerun mode is typically used when an independent clock source is required, or immediately following system
power-up before network synchronization is achieved.
In Freerun mode, the ZL30100 provides timing and synchronization signals which are based on the master clock
frequency (supplied to OSCi pin) only, and are not synchronized to the reference input signals.
The Freerun accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a
±
32 ppm
output clock is required, the master clock must also be
±
32 ppm. See Applications - Section 6.2, “Master Clock“ on
page 23.
BW_SEL
Detected REF Frequency
Loop Filter Bandwidth
Phase Slope Limiting
0
any
1.8 Hz
61
μ
s/s
1
8 kHz
58 Hz
9.5 ms/s
1
1.544 MHz, 2.048 MHz,
8.192 MHz, 16.384 MHz
922 Hz
9.5 ms/s
Table 2 - Loop Filter Settings
OUT_SEL
Generated Clocks
Generated Frame Pulses
0
C1.5o, C2o, C4o, C8o, C16o
F4o, F8o, F16o
1
C1.5o, C2o, C16o, C32o, C65o
F16o, F32o, F65o
Table 3 - Clock and Frame Pulse Selection
MODE_SEL1
MODE_SEL0
Mode
0
0
Normal (with automatic Holdover)
0
1
Holdover
1
0
Freerun
1
1
reserved (must not be used)
Table 4 - Operating Modes
相關PDF資料 |
PDF描述 |
|---|---|
| ZL30100 | T1/E1 System Synchronizer |
| ZL30100QDC | T1/E1 System Synchronizer |
| ZL30101QDG1 | T1/E1 Stratum 3 System Synchronizer |
| ZL30101 | T1/E1 Stratum 3 System Synchronizer |
| ZL30101QDC | T1/E1 Stratum 3 System Synchronizer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30101 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 3 System Synchronizer |
| ZL30101_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 3 System Synchronizer |
| ZL30101QDC | 制造商:Microsemi Corporation 功能描述: |
| ZL30101QDG1 | 制造商:Microsemi Corporation 功能描述:SYS SYNCHRONIZER 64TQFP - Trays |
| ZL30102 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
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