參數(shù)資料
型號(hào): ZL30100QDG1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: T1/E1 System Synchronizer
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP64
封裝: 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64
文件頁數(shù): 25/36頁
文件大小: 346K
代理商: ZL30100QDG1
ZL30100
Data Sheet
25
Zarlink Semiconductor Inc.
Figure 13 - Crystal Oscillator Circuit
6.3 Power Up Sequence
The ZL30100 requires that the 3.3 V rail is not powered-up later than the 1.8 V rail. This is to prevent the risk of
latch-up due to the presence of parasitic diodes in the IO pads.
Two options are given:
1. Power up the 3.3 V rail fully first, then power up the 1.8 V rail
2. Power up the 3.3 V rail and 1.8 V rail simultaneously, ensuring that the 3.3 V rail voltage is never lower than the
1.8 V rail voltage minus a few hundred millivolts (e.g., by using a schottky diode or controlled slew rate)
OSCo
1 M
20 MHz
ZL30100
OSCi
100
1 μH
The 100
resistor and the 1 μH inductor may improve
stability and are optional.
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