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| 型號(hào)： | XRT94L31IB-L |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 45/133頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MAPPER DS3/E3/STS-1 504TBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 應(yīng)用： | 網(wǎng)絡(luò)切換 |
| 接口： | 總線 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 封裝/外殼： | 504-LBGA |
| 供應(yīng)商設(shè)備封裝： | 504-TBGA（35x35） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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XRT94L31
19
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
AD1
RxD_C1J1
I
TTL
Receive STS-3/STM-1 Telecom Bus Interface - C1/J1 Byte Phase
Indicator Input Signal:
This input pin should be pulsed "High" during both of the following condi-
tions.
a. Coincident to whenever the C1/J0 byte (within the incoming STS-
3/STM-1 signal) is being applied to the Receive STS-3/STM-1
Telecom Bus - Data Input pins (RXD_D[7:0]).
b. Coincident to whenever the J1 byte(s) (within the incoming STS-3/
STM-1 signal) is being applied to the Receive STS-3/STM-1
Telecom Bus - Data Input pins (RXD_D[7:0]) input.
NOTE: This input pin should be pulled "Low" during all other times.
AB3
RxD_DP
I
TTL
Receive STS-3/STM-1 Telecom Bus Interface - Parity Input pin:
This input pin can be configured to function as one of the following.
The EVEN or ODD parity value of the bits (within the incoming STS-3/
STM-1 signal) which are currently being input via the RXD_D[7:0] input
pins.
The EVEN or ODD parity value of the bits (within the incoming STS-3/
STM-1 signal) which are being input via the RXD_D[7:0] input and the
states of the RXD_PL and RXD_C1J1 input pins.
The Receive STS-3/STM-1 Telecom Bus Interface block will use this
input signal to compute and verify the Parity of each byte within the
incoming STS-3/STM-1 data-stream.
NOTES:
1. Any one of these configuration selections can be made by
writing the appropriate value into the Telecom Bus Control
register (Address Location = 0x0137).
2. Tie this input pin to GND if the STS-3/STM-1 Telecom Bus
Interface is disabled.
W1
RxD_ALARM
I
TTL
Receive STS-3/STM-1 Telecom Bus Interface - Alarm Indicator
Input:
This input pin should be pulsed "High" for one RxD_CLK period coinci-
dent to whenever the Receive STS-3/STM-1 Telecom Bus Interface is
accepting a byte from an incoming STS-1 or STS-3c signal (via the
RxD_D[7:0] input pins) that is carrying the AIS-P indicator.
This input pin should be held at a logic "Low" at all other times.
NOTES:
1. If the RxD_ALARM input signal pulses "High" for any given
STS-1 signal (within the incoming STS-3), the XRT94L31 will
automatically declare the AIS-P defect condition for that STS-1
or STS-3c channel.
2. Tie this input pin to GND, if the STS-3/STM-1 Telecom Bus
Interface is disabled.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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| XRT94L33 | 制造商:EXAR 制造商全稱:EXAR 功能描述:-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - SONET REGISTERS |
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| XRT94L33_2 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - SDH REGISTERS |
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