REV. 1.0.1 AC9 RxE1F1E2 O CMOS Receive - Order-Wire Output Port - Output Pin: This " />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 117/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
84
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
AC9
RxE1F1E2
O
CMOS
Receive - Order-Wire Output Port - Output Pin:
This output pin, along with RxE1F1E2Val, RxE1F1F2FP, and the RxTO-
HClk output pins function as the Receive Order-Wire Output Port of the
XRT94L31.
This pin outputs the contents of the Order-Wire bytes (e.g., the E1, F1
and E2 bytes) within the incoming STS-3 data-stream.
The Receive Order-Wire Output port will pulse the RxE1F1E2FP output
pin "High" (for one period of RxTOHClk) coincident to when the very first
bit (of the E1 byte) is being output via the RxE1F1E2 output pin. Addi-
tionally, the Receive Order-Wire Output port will also assert the
RxE1F1E2Val output pin, in order to indicate that the data, residing on
the RxE1F1E2 output pin is valid Order-Wire byte.
The Receive Order-Wire output port will update the RxE1F1E2Val, the
RxE1F1E2FP and the RxE1F1E2 output pins upon the falling edge of
the RxTOHClk output pin.
The Receive Order-Wire circuitry that is interfaced to this output pin, and
the RxE1F1E2Val, the RxE1F1E2 and the RxTOHClk pins is suppose to
do the following.
It should continuously sample and monitor the state of the RxE1F1E2Val
and RxE1F1E2FP output pins upon the rising edge of RxTOHClk.
Anytime the Order-wire circuitry samples the RxE1F1E2Val and
RxE1F1E2FP output pins "High", it should begin to sample and latch the
contents of this output pin (as a valid Order-Wire bit) into the Order-Wire
circuitry.
The Order-Wire circuitry should continue to sample and latch the con-
tents of the output pin until the RxE1F2E2Val output pin is sampled
"Low".
AC8
RxSDCC
O
CMOS
Receive - Section DCC Output Port - Output Pin:
This output pin, along with RxSDCCVAL and the RxTOHClk output pins
function as the Receive Section DCC output port of the XRT94L31.
This pin outputs the contents of the Section DCC (e.g., the D1, D2 and
D3 bytes), within the incoming STS-3 data-stream.
The Receive Section DCC Output port will assert the RxSDCCVAL out-
put pin, in order to indicate that the data, residing on the RxSDCC output
pin is a valid Section DCC byte. The Receive Section DCC output port
will update the RxSDCCVAL and the RxSDCC output pins upon the fall-
ing edge of the RxTOHClk output pin.
The Section DCC HDLC circuitry that is interfaced to this output pin, the
RxSDCCVAL and the RxTOHClk pins is suppose to do the following.
It should continuously sample and monitor the state of the RxSDCCVAL
output pin upon the rising edge of RxTOHClk.
Anytime the Section DCC HDLC circuitry samples the RxSDCCVAL out-
put pin "High", it should sample and latch the contents of this output pin
(as a valid Section DCC bit) into the Section DCC HDLC circuitry.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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