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參數(shù)資料
| 型號： | XRT73L04BIV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 47/64頁 |
| 文件大小： | 0K |
| 描述： | IC LIU E3/DS3/STS-1 4CH 144LQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/4 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
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XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
47
4.0
DIAGNOSTIC FEATURES OF THE
XRT73L04B
The XRT73L04B supports equipment diagnostic ac-
tivities by supporting the following Loop-Back modes
within each channel.
Analog Local Loop-Back.
Digital Local Loop-Back
Remote Loop-Back
NOTE: In this data sheet we use the convention that Chan-
nel(n) refers to either channel 0, 1, 2 or 3. Similarly, specific
input and output pins uses this convention to denote which
channel it is associated with.
4.1
THE ANALOG LOCAL LOOP-BACK MODE
When a given channel is configured to operate in the
Analog Local Loop-Back Mode, the channel ignores
any signals that are input to its RTIP_(n) and
RRing_(n) input pins. The Transmitting Terminal
Equipment transmits clock and data into this channel
via the TPData_(n), TNData_(n) and TxClk_(n) input
pins. This data is processed through the Transmit
Clock Duty Cycle Adjust PLL and the HDB3/B3ZS
Encoder. Finally, this data is output to the line via the
TTIP_(n) and TRing_(n) output pins. Additionally, this
data which is being output via the TTIP_(n) and
TRing_(n) output pins is also looped back into the At-
tenuator/Receive Equalizer Block. Consequently, this
data is processed through the entire Receive Section
of the channel. After this post-Loop-Back data has
been processed through the Receive Section it out-
puts to the Near-End Receiving Terminal Equipment
via the RPOS_(n), RNEG_(n) and RxClk_(n) output
pins.
Figure 33 illustrates the path that the data takes when
the channel is configured to operate in the Analog Lo-
cal Loop-Back Mode.
Configure a given channel to operate in the Analog
Local Loop-Back Mode by employing either one of
the following two steps
a. Operating in the HOST Mode
ters and Addresses for the different channels.
To configure Channel (n) to operate in the Analog Lo-
cal Loop-Back Mode, write a “1" into the LLB_(n) bit-
field and a "0" into the RLB_(n) bit-field within Com-
mand Register CR4.
FIGURE 33. A CHANNEL OPERATING IN THE ANALOG LOCAL LOOP-BACK MODE
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR_(n)
SDI
SDO
SClk
CS/(SR/DR)
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
Notes: 1. (n) = 0, 1, 2, or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in
Hardware Mode.
RLOL_(n) EXClk_(n)
Device
Monitor
MTIP_(n)
MRing_(n)
Transmit
Logic
Duty Cycle Adjust
TxLEV_(n)
TxOFF_(n)
DMO_(n)
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Analog Local
Loop-Back Path
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