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參數(shù)資料
| 型號： | XRT73L04BIV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 27/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 4CH 144LQFP |
| 標準包裝： | 60 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
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XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
29
TxClk_(n) is the clock signal that is of the selected
data rate frequency, E3 = 34.368 MHz, DS3 = 44.736
MHz and STS-1 = 51.84 MHz. If the Transmit Sec-
tion samples a "1" on the TPData_(n) input pin, then
the Transmit Section of the device generates a posi-
tive polarity pulse via the TTIP_(n) and TRing_(n)
output pins across a 1:1 transformer. If the Transmit
Section samples a "1" on the TNData_(n) input pin,
then the Transmit Section of the device generates a
negative polarity pulse via the TTIP_(n) and
TRing_(n) output pins across a 1:1 transformer.
2.1.2
Accepting Single-Rail Data from the Ter-
minal Equipment
To transmit data in a Single-Rail data from the Termi-
nal Equipment, configure the XRT73L04B in the
HOST Mode.
To Configure Channel(n) to accept Single-Rail Da-
ta from the Terminal Equipment:
Write a "1" into the (SR/DR)_(n) bit-field, within Com-
mand Register CR3-(n) shown below. (Please refer
toTable 2 for the Address of the individual (n) chan-
nel.
The Transmit Section (of each channel) samples this
input pin on the falling edge of the TxClk_(n) clock
signal and encodes this data into the appropriate bi-
polar line signal across the TTIP_(n) and TRing_(n)
output pins.
NOTES:
1. In this mode, the Transmit Logic Block ignores the
TNData_(n) input pin.
2. If the Transmit Section of a given channel is config-
ured to accept Single-Rail data from the Terminal
Equipment, the B3ZS/HDB3 Encoder must be
enabled.
Figure 16 Illustrates the behavior of the TPData_(n)
and TxClk_(n) signals when the Transmit Logic Block
has been configured to accept Single-Rail data from
the Terminal Equipment.
2.2
THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIR-
CUITRY
The on-chip Pulse-Shaping circuitry within the Trans-
mit Section of each Channel in the XRT73L04B gen-
erates pulses of the appropriate shapes and width to
meet the applicable pulse template requirements.
The widths of these output pulses are defined by the
width of the half-period pulses within the TxClk_(n)
signal.
However, if the widths of the pulses within the
TxClk_(n) clock signal are allowed to vary significant-
ly, this could jeopardize the chip’s ability to generate
Transmit Output pulses of the appropriate width and
thereby not meet the Pulse Template requirement
specification. Consequently, the chip’s ability to gen-
erate compliant pulses could depend upon the duty
cycle of the clock signal applied to the TxClk_(n) input
pin.
The Transmit Clock Duty Cycle Adjust Circuitry ac-
cepts clock pulses via the TxClk_(n) input pin at duty
cycles ranging from 30% to 70% and converts them
to a 50% duty cycle.
2.3
THE HDB3/B3ZS ENCODER BLOCK
The purpose of the HDB3/B3ZS Encoder Block is to
aid in the Clock Recovery process at the Remote Ter-
minal Equipment by ensuring an upper limit on the
number of consecutive zeros that can exist within the
line signal.
2.3.1
B3ZS Encoding
If the XRT73L04B has been configured to operate in
the DS3 or SONET STS-1 Modes, then the HDB3/
B3ZS Encoder blocks operate in the B3ZS Mode.
When the Encoder is operating in this mode, it pars-
es through and searches the Transmit Binary Data
Stream from the Transmit Logic Block for the occur-
COMMAND REGISTER CR3-(n)
D4
D3
D2
D1
D0
(SR/DR)_(n) LOSMUT_(n) RxOFF RxClk_(n)INV Reserved
1x
x
FIGURE 16. THE BEHAVIOR OF THE TPDATA AND TXCLK INPUT SGNALS, WHILE THE TRANSMIT LOGIC BLOCK IS
ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT
TxClk
TPData
Data
1
0
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