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參數(shù)資料
| 型號： | XRT73L04BIV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 37/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 4CH 144LQFP |
| 標準包裝： | 60 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
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XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
38
3.3
CLOCK RECOVERY PLL
The purpose of the Clock Recovery PLL is to track
the incoming Dual-Rail data stream and to derive and
generate a recovered clock signal.
It is important to note that the Clock Recovery PLL re-
quires a line rate clock signal at the EXClk_(n) input
pin.
The Clock Recovery PLL operates in one of two
modes:
The Training Mode.
The Data/Clock Recovery Mode
3.3.1
The Training Mode
If a given channel is not receiving a line signal via the
RTIP and RRing input pins, or if the frequency differ-
ence between the line signal and that applied via the
EXClk_(n) input pin exceeds 0.5%, then the channel
operates in the Training Mode. When the channel is
operating in the Training Mode, it does the following:
a. Declare a Loss of Lock indication by toggling its
respective RLOL_(n) output pin “High".
b. Output a clock signal via the RxClk_(n) output
pins which is derived from the signal applied to
the EXClk_(n) input pin.
3.3.2
The Data/Clock Recovery Mode
If the frequency difference between the line signal
and that applied via the EXClk_(n) input pin is less
than 0.5%, then the channel operates in the Data/
Clock Recovery mode. In this mode, the Clock Re-
covery PLL locks onto the line signal via the RTIP
and RRing input pins.
3.4
THE HDB3/B3ZS DECODER
The Remote Transmitting Terminal typically encodes
the line signal into some sort of Zero Suppression
Line Code (e.g., HDB3 for E3, and B3ZS for DS3 and
STS-1). The purpose of this encoding activity was to
aid in the Clock Recovery process of this data within
the Near-End Receiving Terminal. However, once the
data has made it across the E3, DS3 or STS-1 Trans-
port Medium and has been recovered by the Clock
Recovery PLL, it is now necessary to restore the orig-
inal content of the data. Hence, the purpose of the
HDB3/B3ZS Decoding block is to restore the data
transmitted over the E3, DS3 or STS-1 line to its orig-
inal content prior to Zero Suppression Coding.
3.4.1
B3ZS Decoding (DS3/STS-1 Applications)
If the XRT73L04B is configured to operate in the DS3
or STS-1 Modes, then the HDB3/B3ZS Decoding
Blocks performs B3ZS Decoding. When the Decod-
ers are operating in this mode, each of the Decoders
parses through its respective incoming Dual-Rail data
and checks for the occurrence of either a “00V" or a
"B0V" pattern. If the B3ZS Decoder detects this par-
ticular pattern, then it substitutes these bits with a
"000" pattern.
NOTE: If the B3ZS Decoder detects any bipolar violations
that is not in accordance with the B3ZS Line Code format,
or if the B3ZS Decoder detects a string of 3 (or more) con-
secutive "0’s” in the incoming line signal, then the B3ZS
Decoder flags this event as a Line Code Violation by puls-
ing the LCV output pin “High".
Figure 24 illustrates the B3ZS Decoder at work with
two separate Zero Suppression patterns in the in-
coming Dual-Rail Data Stream.
3.4.2
HDB3 Decoding (E3 Applications)
If the XRT73L04B is configured to operate in the E3
Mode, then each of the HDB3/B3ZS Decoding Blocks
performs HDB3 Decoding. When the Decoders are
operating in this mode, they each parse through the
incoming Dual-Rail data and check for the occurrence
of either a "000V" or a "B00V" pattern. If the HDB3
FIGURE 24. AN EXAMPLE OF B3ZS DECODING
Data
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RPOS
RNEG
0 0
V
Line Signal
B
0 V
RCLK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
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| XRT73L06IQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
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