參數(shù)資料
型號(hào): XRT73L04BIV-F
廠商: Exar Corporation
文件頁(yè)數(shù): 1/64頁(yè)
文件大?。?/td> 0K
描述: IC LIU E3/DS3/STS-1 4CH 144LQFP
標(biāo)準(zhǔn)包裝: 60
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 4/4
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
OCTOBER 2003
REV. 1.0.1
GENERAL DESCRIPTION
The XRT73L04B, 4-Channel, DS3/E3/STS-1 Line In-
terface Unit is a low power CMOS version of the
XRT73L04A and consists of four independent line
transmitters and receivers integrated on a single chip
designed for DS3, E3 or SONET STS-1 applications.
Each channel of the XRT73L04B can be configured
to support the E3 (34.368 Mbps), DS3 (44.736 Mbps)
or the SONET STS-1 (51.84 Mbps) rates. Each
channel can be configured to operate in a mode/data
rate that is independent of the other channels.
In the transmit direction, each channel encodes input
data to either B3ZS (DS3/STS-1) or HDB3 (E3) for-
mat and converts the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction, the XRT73L04B performs
equalization on incoming signals, performs Clock Re-
covery, decodes data from either B3ZS or HDB3 for-
mat, converts the receive data into TTL/CMOS for-
mat, checks for LOS or LOL conditions and detects
and declares the occurrence of Line Code Violations.
FEATURES
Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L04A
Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
Contains a 4-Wire Microprocessor Serial Interface
Full Loop-Back Capability
Transmit and Receive Power Down Modes
Full Redundancy Support
Uses Minimum External components
Single +3.3V Power Supply
Low Power CMOS design
5V tolerant I/O
-40°C to +85°C Operating Temperature Range
Available in a Thermally Enhanced 144 pin LQFP
package
APPLICATIONS
Digital Cross Connect Systems
CSU/DSU Equipment
Routers
Fiber Optic Terminals
Multiplexers
ATM Switches
FIGURE 1. XRT73L04B BLOCK DIAGRAM
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
TxLEV_(n)
TxOFF
Channel 2
AGC/
Equalizer
Serial
Processor
Interface
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR
SDI
SDO
SClk
CS/(SR/DR)
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
Channel 0
Channel 1
Notes: 1. (n) = 0, 1, 2 , or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in
Hardware Mode.
Device
Monitor
MTIP_(n)
MRing_(n)
DMO_(n)
Transmit
Logic
Duty Cycle Adjust
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
E3_(n)
STS-1/DS3_(n)
Host/(HW)
RLOL_(n) EXClk_(n)
RxOFF
RxClkINV
RxClk_(n)
RPOS_(n)
RNEG_(n)/
(LCV_(n))
Channel 3
Tx
Control
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