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| 型號： | XRT72L52IQTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 438/488頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRAMER DS3/E3 2CH 160QFP |
| 產(chǎn)品變化通告： | XRT72Lx Series Obsolescence 02/May/2012 |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 控制器類型： | DS3/E3 調(diào)幀器 |
| 電源電壓： | 3.3V |
| 電流 - 電源： | 100mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-PQFP（28x28） |
| 包裝： | 帶卷 (TR) |
XRT72L52
37
REV. 1.0.3
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
2.0
THE MICROPROCESSOR INTERFACE BLOCK
The Microprocessor Interface section supports the following operations for communication between the local
Microprocessor (P) and the Framer IC:
The writing of configuration data into the Framer on-chip addressable registers.
The writing of an outbound PMDL (Path Maintenance Data Link) message into the Transmit LAPD Message
buffer.
The Framer IC's generation of an Interrupt Request to the Microprocessor.
The Microprocessor’s servicing of the interrupt request from the Framer IC.
The monitoring of the system's health by periodically reading the on-chip Performance Monitor registers.
The reading of an inbound PMDL Message from the Receive LAPD Message Buffer.
Receiving and sending FEAC Codes
Figure 21 is a simple block diagram of the Microprocessor Interface Section within the Framer..
2.1
The Microprocessor Interface Block Signasl
The Framer IC may be configured into a wide variety of different operating modes and have its performance
monitored by software through a standard microprocessor interface using data, address and control signals.
The local Microprocessor configures the Framer IC into a desired operating mode by writing data into specific
addressables, on-chip Read/Write registers, or on-chip RAM.
The microprocessor interface provides the
signals which are required for a general purpose microprocessor to read or write data into these registers. The
Microprocessor Interface also supports polled and interrupt driven environments. These interface signals are
described below in Table 1, Table 2, and Table 3. The microprocessor interface can be configured to operate
in the Motorola Mode or in the Intel mode. In the Motorola mode, the control signals function as required by the
Motorola 68000 family of microprocessors. Likewise, in the Intel Mode, these control signals function as
required by the Intel family of microprocessors.
FIGURE 21. BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK
A[8:0]
WR_R/W
RD_DS
CS
ALE_AS
Reset
Int
D[7:0]
MOTO
RDY_DTCK
M icroprocessor
&
Program m able
Registers
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