XRT72L52
445
REV. 1.0.3
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
TABLE 97: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT
INTERFACE BLOCK
SIGNAL NAME
TYPE
DESCRIPTION
RxSer
Output
Receive Serial Payload Data Output pin:
If the user opts to operate the XRT72L52 in the serial mode, then the chip will output the pay-
load data, of the incoming E3 frames, via this pin. The XRT72L52 will output this data upon
the rising edge of RxClk.
The user is advised to design the Terminal Equipment such that it will sample this data on the
rising edge of RxClk.
NOTE: This signal is only active if the NibIntfinput pin is pulled "Low".
RxNib[3:0]
Output
Receive Nibble-Parallel Payload Data Output pins:
If the user opts to operate the XRT72L52 in the nibble-parallel mode, then the chip will output
the payload data, of the incoming E3 frames, via these pins. The XRT72L52 will output data
via these pins, upon the falling edge of the RxClk output pin.
The user is advised to design the Terminal Equipment such that it will sample this data upon
the rising edge of RxClk.
NOTE: These pins are only active if the NibIntfinput pin is pulled "High".
RxClk
Output
Receive Payload Data Output Clock pin:
The exact behavior of this signal depends upon whether the XRT72L52 is operating in the
Serial or in the Nibble-Parallel-Mode.
Serial Mode Operation
In the serial mode, this signal is a 34.368MHz clock output signal. The Receive Payload Data
Output Interface will update the data via the RxSer output pin, upon the rising edge of this
clock signal.
The user is advised to design (or configure) the Terminal Equipment to sample the data on the
RxSer pin, upon the falling edge of this clock signal.
Nibble-Parallel Mode Operation
In this Nibble-Parallel Mode, the XRT72L52 will derive this clock signal, from the RxLineClk
signal. The XRT72L52 will pulse this clock 1060 times for each Inbound E3 frame. The
Receive Payload Data Output Interface will update the data, on the RxNib[3:0] output pins
upon the falling edge of this clock signal.
The user is advised to design (or configure) the Terminal Equipment to sample the data on the
RxNib[3:0] output pins, upon the rising edge of this clock signal