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DS3/E3 FRAMER IC
XRT7250
REV. 1.1.1
147
B. Nibble-Parallel Mode
The XRT7250 will accept the DS3 payload data, from
the Terminal Equipment, in a parallel manner, via the
TxNib[3:0] input pins. The Transmit Terminal Equip-
ment Input Interface will latch this data into its circuit-
ry, on the rising edge of the TxNibClk output signal.
C. Delineation of outbound DS3 Frames
The Transmit Section will use the TxInClk input signal
as its timing reference and will initiate the generation
of DS3 frames, asynchronous with respect to any ex-
ternal signal. The XRT7250 will pulse the TxFrame
output pin "High" whenever it is processing the last
nibble, within a given outbound DS3 frame.
D. Sampling of payload data, from the Terminal
Equipment
In Mode 6, the XRT7250 will sample the data, at the
TxNib[3:0] input pins, on the third rising edge of the
TxInClk clock signal, following a pulse in the TxNibClk
NOTE: The TxNibClk signal from the XRT7250, operates
nominally at 11.184 MHz (e.g., 44.736 MHz divided by 4).
However, for reasons described below, TxNibClk effectively
operates at a "Low"er clock frequency. The Transmit Pay-
load Data Input Interface is only used to accept the payload
data, which is intended to be carried by outbound DS3
frames. The Transmit Payload Data Input Interface is not
designed to accommodate the entire DS3 data stream.
The DS3 Frame consists of 4704 payload bits or 1176
nibbles. Therefore, the XRT7250 will supply 1176 Tx-
NibClk pulses between the rising edges of two con-
secutive TxNibFrame pulses. The DS3 Frame repeti-
tion rate is 9.398kHz. Hence, 1176 TxNibClk pulses
for each DS3 frame period amounts to TxNibClk run-
ning at approximately 11.052 MHz. The method by
which the 1176 TxNibClk pulses are distributed
throughout the DS3 frame period is presented below.
Nominally, the Transmit Section within the XRT7250
will generate a TxNibClk pulse for every 4 RxOutClk
(or TxInClk) periods. However, in 14 cases (within a
DS3 frame period), the Transmit Payload Data Input
Interface will allow 5 TxInClk periods to occur be-
tween two consecutive TxNibClk pulses.
Interfacing the Transmit Payload Data Input Inter-
face block of the XRT7250 to the Terminal Equip-
ment for Mode 6 Operation
Figure 54 presents an illustration of the Transmit Pay-
load Data Input Interface block (within the XRT7250)
being interfaced to the Terminal Equipment, for Mode
6 Operation.
Mode 6, Operation of the Terminal Equipment
In
Figure 54 both the Terminal Equipment and the
XRT7250 will be driven by an external 11.184MHz
clock signal. The Teriminal Equipment will receive
the 11.184MHz clock signal via the
DS3_Nib_Clock_In input pin. The XRT7250 will out-
put the 11.184MHz clock signal via the TxNibClk out-
put pin.
FIGURE 54. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA
INPUT INTERFACE BLOCK OF THE XRT7250 FOR MODE 6 (NIBBLE-PARALLEL/LOCAL-TIMED/FRAME-MASTER)
OPERATION
Terminal Equipment
XRT7250 DS3 Framer
DS3_Data_Out[3:0]
DS3_Nib_Clock_In
Tx_Start_of_Frame
TxNib[3:0]
TxNibClk
TxNibFrame
NibInt
VCC
4
44.736MHz Clock Source
TxInClk
11.184MHz