
XRT7250
DS3/E3 FRAMER IC
á
REV. 1.1.1
120
Therefore, if the user is using either one of these in-
puts as an interrupt request input, then the user must
ensure that the appropriate interrupt service routine
or unconditional branch instruction (to the interrupt
service routine) is located at one of these address lo-
cations.
If the 8051 Microcontroller IC is required to interface
to external components in the data memory space of
sizes greater than 256 bytes, then both Ports 0 and 2
must be used as the address and data lines. Port 0
will function as a multiplexed address/data bus. Dur-
ing the first half of a memory cycle, Port 0 will operate
as the lower address byte. During the second half of
the memory cycle, Port 0 will operate as the bi-direc-
tional data bus. Port 2 will be used as the upper ad-
dress byte. ALE and the use of a 74HC373 transpar-
ent latch device can be used to de-multiplex the Ad-
dress and Data bus signals.
Figure 37 presents a schematic illustrating how the
XRT7250 DS3/E3 Framer can be interfaced to the
8051 Microcontroller IC.
The circuitry in
Figure 37 will function as follows, dur-
ing a Framer-request interrupt. The Framer device
would request an interrupt from the CPU by asserting
its active low INT output pin. This will cause the
INT0* input pin of the CPU to go "Low”. When this
happens the 8051 CPU will finish executing its cur-
rent instruction, and will then branch program control
to the Framer Device interrupt service routine. In the
case of
Figure 37, the interrupt service routine will be
located in 0x0003 in code memory. The 8051 CPU
TABLE 13: INTERRUPT SERVICE ROUTINE LOCATION (IN CODE MEMORY) FOR THE INT0* AND INT1* INTERRUPT
INPUT PINS
INTERRUPT PIN
BRANCH TO LOCATION (IN SYSTEM MEMORY)
INT0*
0x0003
INT1*
0x0013
FIGURE 37. SCHEMATIC DEPICTING HOW TO INTERFACE THE XRT7250 DS3/E3 FRAMER IC TO THE 8051 MICRO-
CONTROLLER
+5V
U2
8051
WR
16
RD
17
AD0
39
AD1
38
AD2
37
AD3
36
AD4
35
AD5
34
AD6
33
AD7
32
ALE
30
A8
21
A9
22
A10
23
A11
24
A12
25
A13
26
A14
27
A15
28
INT0
12
INT1
13
U1
XRT7250
RESET
28
RDB_DS
29
ALE_AS
31
INT
13
CS
8
WRB_RW
7
D0
32
D1
33
D2
34
D3
35
D4
36
D5
37
D6
38
D7
39
A0
14
A1
15
A2
16
A3
17
A4
18
A5
19
A6
20
A7
21
A8
22
MOTO/INTEL
27
Rdy_Dtck
6
U?
74HC373
D0
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
OC
1
G
11
Q0
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
to Address Decoder
from Address Decoder
ALE
INTERRUPT
RESET Command Circuitry