參數(shù)資料
型號(hào): XRS10L120
廠商: Exar Corporation
英文描述: SERIAL ATA II: 1:2 PORT MULTIPLIER
中文描述: 串行ATA II:1:2端口倍增器
文件頁數(shù): 27/52頁
文件大?。?/td> 399K
代理商: XRS10L120
PRELIMINARY
XRS10L120
25
REV. P1.0.1
SERIAL ATA II: 1:2 PORT MULTIPLIER
N.000D
N.002D
7:6
7:6
Reserved
RO
-
Reserved
5:0
5:0
MaxWakeWidth0
MaxWakeWidth1
RW
010110
Upper bound count of idle for COMINIT/COM-
RESET
N.000E
N.002E
7:6
Reserved
RO
-
Reserved
5:0
MinWakeWidth0[5:0]
MinWakeWidth1[5:0]
RW
000100
Lower bound count of idle for COMWAKE
N.000F
N.002F
7:6
Reserved
RO
-
Reserved
5:0
MaxWakeWidth0[5:0]
MaxWakeWidth1[5:0]
000111
Upper bound count of idle for COMWAKE
N.0010
N.0030
7:6
Reserved
RO
-
Reserved
5:3
rcvRef0[2:0]
rcvRef1[2:0]
RW
011
Percent of full swing that TX must reach during
Receiver Detect to count as receiver present
(not applicable to SATA PHY macros)
2:0
squelchdivsel[2:0]
010
Value by which to divide squelch clock
000 = divide by 1
001 = divide by 2
010 = divide by 4
011 = divide by 6
100 = divide by 8
101 = divide by 10
110 = divide by 12
111 = divide by 14
N.0011
N.0031
7:0
rcvdetdelay0[10:0]
(lower 8 bits)
Number of SYSCLK cycles to wait between
assertion of RECDET and clocking comparator
N.0012
N.0032
7:3
Reserved
RO
-
Reserved
2:0
rcvdetdelay0[10:0]
(upper 3 bits)
Number of SYSCLK cycles to wait between
assertion of RECDET and clocking comparator
for receiver detect (not applicable to SATA PHY
macros)
T
ABLE
9: T
RANSMIT
/R
ECEIVE
L
ANE
R
EGISTERS
(MDIO D
EVICE
1
AND
2)
A
DDRESS
H
EX
B
IT
(
S
)
N
AME
R/W
D
EFAULT
D
ESCRPTION
相關(guān)PDF資料
PDF描述
XRS10L120IV SERIAL ATA II: 1:2 PORT MULTIPLIER
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