參數(shù)資料
型號(hào): XRS10L120
廠商: Exar Corporation
英文描述: SERIAL ATA II: 1:2 PORT MULTIPLIER
中文描述: 串行ATA II:1:2端口倍增器
文件頁(yè)數(shù): 19/52頁(yè)
文件大小: 399K
代理商: XRS10L120
PRELIMINARY
XRS10L120
17
REV. P1.0.1
SERIAL ATA II: 1:2 PORT MULTIPLIER
T
ABLE
3: S
ERIAL
ATA L
INK
S
PECIFICATIONS
N
AME
D
ESCRIPTION
M
IN
.
N
OM
M
AX
U
NITS
t
BIT,XS
Bit Time
670
-
333
ps
J
XR1
Input Jitter Tolerance Mask at signal crossover
0.32
-
-
UI
J
XR1,DJ
Deterministic jitter tolerance at signal crossover
0.18
-
-
UI
J
XT1
Output jitter mask at signal crossover
-
-
0.15
UI
J
XT1,DJ
Deterministic output jitter at signal crossover
-
-
0.07
UI
t
R
/t
F
Input signal rise/fall times (20% - 80%)
0.2
-
0.46
UI
t
QR
/t
QF
Output signal rise/fall times (20% - 80%)
0.2
-
0.41
UI
t
TOL,RX1
RX to sysclock frequency offset tolerance
-5350
0
350
ppm
V
IN
Input swing, differential peak-peak
175
-
1600
mV
V
SW2
Output swing, differential peak-peak
800
-
1200
mV
V
IN,IDLE
No swing detection threshold
65
120
155
mV
R
IN,DIFF
Differential mode input resistance
85
100
115
mV
R
IN,CM3
Common mode input resistance
40
50
60
Ω
R
IN,OFF
Common mode input resistance, no power
200
-
-
k
Ω
R
IN,XS
Output termination resistance
40
50
60
Ω
S
11,IN,DIFF
Differential input return loss, 50MHz - 1.5GHz
12
-
-
dB
S
11,IN,CM
Common mode input return loss 50MHz-1.5GHz
6
-
-
dB
S
22,OUT,DIFF
Differential output return loss 50MHz-1.5GHz
12
-
-
dB
S
22,OUT,CM
Common mode output return loss 50MHz-1.5GHz
6
-
-
dB
t
S,REG
Setup time for register port
1.5
-
-
ns
t
H,REG
Hold time for register port
1.5
-
-
ns
t
Q,REG
Clock to Q time for register port
0
-
2
ns
t
CYC,REG
Register port clock cycle time
10
-
-
ns
t
HI,REG
R register port clock high time
4
-
-
ns
t
LO,REG
Register port clock low time
4
-
-
ns
t
RF,REG
Register port input rise/fall time
-
-
0.5
ns
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