參數(shù)資料
型號(hào)： XCV800
廠商： Xilinx, Inc.
英文描述： Virtex 2.5 V Field Programmable Gate Arrays(Virtex 2.5V現(xiàn)場(chǎng)可編程門(mén)陣列)
中文描述： 2.5伏的Virtex現(xiàn)場(chǎng)可編程門(mén)陣列（的Virtex 2.5V的現(xiàn)場(chǎng)可編程門(mén)陣列）
文件頁(yè)數(shù)： 9/72頁(yè)
文件大?。?/td> 456K
代理商： XCV800
DS003 (v2.4) October 6, 2000 - Final Product Specification
9
Virtex
2.5 V Field Programmable Gate Arrays
R
Dedicated Routing
Some classes of signal require dedicated routing resources
to maximize performance. In the Virtex architecture, dedi-
cated routing resources are provided for two classes of sig-
nal.
Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row, permitting multiple busses within
a row, as shown in
Figure
.
Two dedicated nets per CLB propagate carry signals
vertically to the adjacent CLB.
Global Routing
Global Routing resources distribute clocks and other sig-
nals with very high fanout throughout the device. Virtex
devices include two tiers of global routing resources
referred to as primary global and secondary local clock
routing resources.
The primary global routing resources are four dedicated
global nets with dedicated input pins that are designed
to distribute high-fanout clock signals with minimal
skew. Each global clock net can drive all CLB, IOB, and
block RAM clock pins. The primary global nets may only
be driven by global buffers. There are four global
buffers, one for each global net.
The secondary local clock routing resources consist of
24 backbone lines, 12 across the top of the chip and 12
across bottom. From these lines, up to 12 unique
signals per column can be distributed via the 12
longlines in the column. These secondary resources
are more flexible than the primary resources since they
are not restricted to routing only to clock pins.
X8794b
CLB
GRM
To Adjacent
GRM
To Adjacent
GRM
Direct Connection
To Adjacent
CLB
To Adjacent
GRM
To Adjacent
GRM
Direct Connection
To Adjacent
CLB
Figure 7: Virtex Local Routing
CLB
CLB
CLB
CLB
buft_c.eps
Tri-State
Lines
Figure 8: BUFT Connections to Dedicated Horizontal Bus Lines
相關(guān)PDF資料
PDF描述
XCV812E-6BG404C Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-6BG404I Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-6BG556C Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-6BG556I Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-6BG560C Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCV800-4BG432C 功能描述:IC FPGA 2.5V C-TEMP 432-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789
XCV800-4BG432I 功能描述:IC FPGA 2.5V I-TEMP 432-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789
XCV800-4BG560C 功能描述:IC FPGA 2.5V C-TEMP 560-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789
XCV800-4BG560I 功能描述:IC FPGA 2.5V I-TEMP 560-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789
XCV8004FG676C 制造商:XILINX 功能描述:*
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