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參數(shù)資料
| 型號： | XCV800 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Virtex 2.5 V Field Programmable Gate Arrays(Virtex 2.5V現(xiàn)場可編程門陣列) |
| 中文描述： | 2.5伏的Virtex現(xiàn)場可編程門陣列（的Virtex 2.5V的現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 2/72頁 |
| 文件大小： | 456K |
| 代理商： | XCV800 |
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Virtex
2.5 V Field Programmable Gate Arrays
2
DS003 (v2.4) October 6, 2000 - Final Product Specification
R
Virtex Architecture
Virtex devices feature a flexible, regular architecture that
comprises an array of configurable logic blocks (CLBs) sur-
rounded by programmable input/output blocks (IOBs), all
interconnected by a rich hierarchy of fast, versatile routing
resources. The abundance of routing resources permits the
Virtex family to accommodate even the largest and most
complex designs.
Virtex FPGAs are SRAM-based, and are customized by
loading configuration data into internal memory cells. In
some modes, the FPGA reads its own configuration data
from an external PROM (master serial mode). Otherwise,
the configuration data is written into the FPGA (Select-
MAP
, slave serial, and JTAG modes).
The standard Xilinx Foundation
and Alliance Series
Development systems deliver complete design support for
Virtex, covering every aspect from behavioral and sche-
matic entry, through simulation, automatic design transla-
tion and implementation, to the creation, downloading, and
readback of a configuration bit stream.
Higher Performance
Virtex devices provide better performance than previous
generations of FPGA. Designs can achieve synchronous
system clock rates up to 200 MHz including I/O. Virtex
inputs and outputs comply fully with PCI specifications, and
interfaces can be implemented that operate at 33 MHz or
66 MHz. Additionally, Virtex supports the hot-swapping
requirements of Compact PCI.
Xilinx thoroughly benchmarked the Virtex family. While per-
formance is design-dependent, many designs operated
internally at speeds in excess of 100 MHz and can achieve
200 MHz.
Table 2
shows performance data for representa-
tive circuits, using worst-case timing parameters.
Architectural Description
Virtex Array
The Virtex user-programmable gate array, shown in
Figure 1
, comprises two major configurable elements: con-
figurable logic blocks (CLBs) and input/output blocks
(IOBs).
CLBs provide the functional elements for constructing
logic
IOBs provide the interface between the package pins
and the CLBs
CLBs interconnect through a general routing matrix (GRM).
The GRM comprises an array of routing switches located at
the intersections of horizontal and vertical routing chan-
nels. Each CLB nests into a VersaBlock
that also pro-
vides local routing resources to connect the CLB to the
GRM.
The VersaRing
I/O interface provides additional routing
resources around the periphery of the device. This routing
improves I/O routability and facilitates pin locking.
The Virtex architecture also includes the following circuits
that connect to the GRM.
Dedicated block memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
3-State buffers (BUFTs) associated with each CLB that
drive dedicated segmentable horizontal routing
resources
Values stored in static memory cells control the config-
urable logic elements and interconnect resources. These
values load into the memory cells on power-up, and can
reload if necessary to change the function of the device.
Table 2: Performance for Common Circuit Functions
Function
Bits
Virtex -6
Register-to-Register
Adder
16
64
8 x 8
16 x 16
16
64
5.0 ns
7.2 ns
5.1 ns
6.0 ns
4.4 ns
6.4 ns
5.4 ns
4.1 ns
5.0 ns
6.9 ns
Pipelined Multiplier
Address Decoder
16:1 Multiplexer
Parity Tree
9
18
36
Chip-to-Chip
HSTL Class IV
LVTTL,16mA, fast slew
200 MHz
180 MHz
vao_b.eps
IOBs
IOBs
I
I
DLL
DLL
DLL
DLL
VersaRing
V
VersaRing
V
CLBs
B
B
Figure 1: Virtex Architecture Overview
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XCV800-4BG432C | 功能描述:IC FPGA 2.5V C-TEMP 432-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應商設備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCV800-4BG432I | 功能描述:IC FPGA 2.5V I-TEMP 432-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應商設備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCV800-4BG560C | 功能描述:IC FPGA 2.5V C-TEMP 560-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應商設備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCV800-4BG560I | 功能描述:IC FPGA 2.5V I-TEMP 560-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應商設備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCV8004FG676C | 制造商:XILINX 功能描述:* |
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