- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375032 > XCV800 (Xilinx, Inc.) Virtex 2.5 V Field Programmable Gate Arrays(Virtex 2.5V現(xiàn)場可編程門陣列) PDF資料下載
參數(shù)資料
| 型號： | XCV800 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Virtex 2.5 V Field Programmable Gate Arrays(Virtex 2.5V現(xiàn)場可編程門陣列) |
| 中文描述： | 2.5伏的Virtex現(xiàn)場可編程門陣列（的Virtex 2.5V的現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 8/72頁 |
| 文件大?。?/td> | 456K |
| 代理商： | XCV800 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
Virtex
2.5 V Field Programmable Gate Arrays
8
DS003 (v2.4) October 6, 2000 - Final Product Specification
R
Table 6
shows the depth and width aspect ratios for the
Block SelectRAM
Table 6: Block SelectRAM Port Aspect Ratios
The Virtex Block SelectRAM also includes dedicated rout-
ing to provide an efficient interface with both CLBs and
other Block SelectRAMs.
Programmable Routing Matrix
It is the longest delay path that limits the speed of any
worst-case design. Consequently, the Virtex routing archi-
tecture and its place-and-route software were defined in a
single optimization process. This joint optimization mini-
mizes long-path delays, and consequently, yields the best
system performance.
The joint optimization also reduces design compilation
times because the architecture is software-friendly. Design
cycles are correspondingly reduced due to shorter design
iteration times.
Local Routing
The VersaBlock provides local routing resources, as shown
in
Figure 7
, providing the following three types of connec-
tions.
Interconnections among the LUTs, flip-flops, and GRM
Internal CLB feedback paths that provide high-speed
connections to LUTs within the same CLB, chaining
them together with minimal routing delay
Direct paths that provide high-speed connections
between horizontally adjacent CLBs, eliminating the
delay of the GRM.
General Purpose Routing
Most Virtex signals are routed on the general purpose rout-
ing, and consequently, the majority of interconnect
resources are associated with this level of the routing hier-
archy. The general routing resources are located in hori-
zontal and vertical routing channels associated with the
rows and columns CLBs. The general-purpose routing
resources are listed below.
Adjacent to each CLB is a General Routing Matrix
(GRM). The GRM is the switch matrix through which
horizontal and vertical routing resources connect, and is
also the means by which the CLB gains access to the
general purpose routing.
24 single-length lines route GRM signals to adjacent
GRMs in each of the four directions.
72 buffered Hex lines route GRM signals to another
GRMs six-blocks away in each one of the four
directions. Organized in a staggered pattern, Hex lines
may be driven only at their endpoints. Hex-line signals
can be accessed either at the endpoints or at the
midpoint (three blocks from the source). One third of the
Hex lines are bidirectional, while the remaining ones
are uni-directional.
12 Longlines are buffered, bidirectional wires that
distribute signals across the device quickly and
efficiently. Vertical Longlines span the full height of the
device, and horizontal ones span the full width of the
device.
I/O Routing
Virtex devices have additional routing resources around
their periphery that form an interface between the CLB
array and the IOBs. This additional routing, called the Ver-
saRing, facilitates pin-swapping and pin-locking, such that
logic redesigns can adapt to existing PCB layouts.
Time-to-market is reduced, since PCBs and other system
components can be manufactured while the logic design is
still in progress.
Width
1
2
4
8
16
Depth
4096
2048
1024
512
256
ADDR Bus
ADDR<11:0>
ADDR<10:0>
ADDR<9:0>
ADDR<8:0>
ADDR<7:0>
Data Bus
DATA<0>
DATA<1:0>
DATA<3:0>
DATA<7:0>
DATA<15:0>
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV812E-6BG404C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-6BG404I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-6BG556C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-6BG556I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-6BG560C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV800-4BG432C | 功能描述:IC FPGA 2.5V C-TEMP 432-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 標(biāo)準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCV800-4BG432I | 功能描述:IC FPGA 2.5V I-TEMP 432-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 標(biāo)準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCV800-4BG560C | 功能描述:IC FPGA 2.5V C-TEMP 560-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 標(biāo)準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCV800-4BG560I | 功能描述:IC FPGA 2.5V I-TEMP 560-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 標(biāo)準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCV8004FG676C | 制造商:XILINX 功能描述:* |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。