參數(shù)資料
型號(hào)： XCV800
廠商： Xilinx, Inc.
英文描述： Virtex 2.5 V Field Programmable Gate Arrays(Virtex 2.5V現(xiàn)場(chǎng)可編程門陣列)
中文描述： 2.5伏的Virtex現(xiàn)場(chǎng)可編程門陣列（的Virtex 2.5V的現(xiàn)場(chǎng)可編程門陣列）
文件頁(yè)數(shù)： 3/72頁(yè)
文件大?。?/td> 456K
代理商： XCV800
DS003 (v2.4) October 6, 2000 - Final Product Specification
3
Virtex
2.5 V Field Programmable Gate Arrays
R
Input/Output Block
The Virtex IOB,
Figure 2
, features SelectIO
inputs and
outputs that support a wide variety of I/O signalling stan-
dards, see
Table 3
.
The three IOB storage elements function either as
edge-triggered D-type flip-flops or as level sensitive
latches. Each IOB has a clock signal (CLK) shared by the
three flip-flops and independent clock enable signals for
each flip-flop.
In addition to the CLK and CE control signals, the three
flip-flops share a Set/Reset (SR). For each flip-flop, this sig-
nal can be independently configured as a synchronous Set,
a synchronous Reset, an asynchronous Preset, or an asyn-
chronous Clear.
The output buffer and all of the IOB control signals have
independent polarity controls.
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. Two
forms of over-voltage protection are provided, one that per-
mits 5 V compliance, and one that does not. For 5 V com-
pliance, a Zener-like structure connected to ground turns
on when the output rises to approximately 6.5 V. When PCI
3.3 V compliance is required, a conventional clamp diode is
connected to the output supply voltage, V
CCO
.
Optional pull-up and pull-down resistors and an optional
weak-keeper circuit are attached to each pad. Prior to con-
figuration, all pins not involved in configuration are forced
into their high-impedance state. The pull-down resistors
and the weak-keeper circuits are inactive, but inputs may
optionally be pulled up.
The activation of pull-up resistors prior to configuration is
controlled on a global basis by the configuration mode pins.
If the pull-up resistors are not activated, all the pins will
float. Consequently, external pull-up or pull-down resistors
must be provided on pins required to be at a well-defined
logic level prior to configuration.
All Virtex IOBs support IEEE 1149.1-compatible boundary
scan testing.
OBUFT
IBUF
Vref
ds022_02_091300
R
LK
CE
CE
I
Q
CE
D
CE
Q
SR
D
CE
Q
SR
D
CE
Q
SR
PAD
Programmable
Delay
Weak
Keeper
Figure 2: Virtex Input/Output Block (IOB)
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XCV800-4BG432I 功能描述:IC FPGA 2.5V I-TEMP 432-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789
XCV800-4BG560C 功能描述:IC FPGA 2.5V C-TEMP 560-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789
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XCV8004FG676C 制造商:XILINX 功能描述:*
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