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參數(shù)資料
| 型號： | XCV800 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Virtex 2.5 V Field Programmable Gate Arrays(Virtex 2.5V現(xiàn)場可編程門陣列) |
| 中文描述： | 2.5伏的Virtex現(xiàn)場可編程門陣列（的Virtex 2.5V的現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 4/72頁 |
| 文件大小： | 456K |
| 代理商： | XCV800 |
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Virtex
2.5 V Field Programmable Gate Arrays
4
DS003 (v2.4) October 6, 2000 - Final Product Specification
R
Input Path
A buffer In the Virtex IOB input path routes the input signal
either directly to internal logic or through an optional input
flip-flop.
An optional delay element at the D-input of this flip-flop
eliminates pad-to-pad hold time. The delay is matched to
the internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of
the low-voltage signalling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, V
REF
. The need to supply V
REF
imposes
constraints on which standards can used in close proximity
to each other.
See
“
I/O Banking
”
on page 4.
There are optional pull-up and pull-down resistors at each
input for use after configuration. Their value is in the range
50
–
100 k
.
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output signal can be
routed to the buffer directly from the internal logic or
through an optional IOB output flip-flop.
The 3-state control of the output can also be routed directly
from the internal logic or through a flip-flip that provides
synchronous enable and disable.
Each output driver can be individually programmed for a
wide range of low-voltage signalling standards. Each out-
put buffer can source up to 24 mA and sink up to 48mA.
Drive strength and slew rate controls minimize bus tran-
sients.
In most signalling standards, the output High voltage
depends on an externally supplied V
CCO
voltage. The need
to supply V
CCO
imposes constraints on which standards
can be used in close proximity to each other.
See
“
I/O
Banking
”
on page 4.
An optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source sig-
nal, the weak keeper holds the signal in its last state if all
drivers are disabled. Maintaining a valid logic level in this
way eliminates bus chatter.
Because the weak-keeper circuit uses the IOB input buffer
to monitor the input level, an appropriate V
REF
voltage must
be provided if the signalling standard requires one. The
provision of this voltage must comply with the I/O banking
rules.
I/O Banking
Some of the I/O standards described above require V
CCO
and/or V
REF
voltages. These voltages externally and con-
nected to device pins that serve groups of IOBs, called
banks. Consequently, restrictions exist about which I/O
standards can be combined within a given bank.
Eight I/O banks result from separating each edge of the
FPGA into two banks, as shown in
Figure 3
. Each bank has
multiple V
CCO
pins, all of which must be connected to the
same voltage. This voltage is determined by the output
standards in use.
Within a bank, output standards may be mixed only if they
use the same V
CCO
. Compatible standards are shown in
Table 4
. GTL and GTL+ appear under all voltages because
their open-drain outputs do not depend on V
CCO
.
Table 3: Supported Select I/O Standards
I/O Standard
Input Reference
Voltage (V
REF
)
N/A
N/A
N/A
N/A
0.8
1.0
0.75
0.9
0.9
1.5
1.25
1.5
1.32
Output Source
Voltage (V
CCO
)
3.3
2.5
3.3
3.3
N/A
N/A
1.5
1.5
1.5
3.3
2.5
3.3
3.3
Board Termination
Voltage (V
TT
)
N/A
N/A
N/A
N/A
1.2
1.5
0.75
1.5
1.5
1.5
1.25
1.5
N/A
5 V Tolerant
LVTTL 2
–
24 mA
LVCMOS2
PCI, 5 V
PCI, 3.3 V
GTL
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL3 Class I &II
SSTL2 Class I & II
CTT
AGP
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
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