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參數(shù)資料
| 型號： | XCV800 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Virtex 2.5 V Field Programmable Gate Arrays(Virtex 2.5V現(xiàn)場可編程門陣列) |
| 中文描述： | 2.5伏的Virtex現(xiàn)場可編程門陣列（的Virtex 2.5V的現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 5/72頁 |
| 文件大?。?/td> | 456K |
| 代理商： | XCV800 |
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DS003 (v2.4) October 6, 2000 - Final Product Specification
5
Virtex
2.5 V Field Programmable Gate Arrays
R
Table 4: Compatible Output Standards
Some input standards require a user-supplied threshold
voltage, V
REF
. In this case, certain user-I/O pins are auto-
matically configured as inputs for the V
REF
voltage. Approx-
imately one in six of the I/O pins in the bank assume this
role.
The V
REF
pins within a bank are interconnected internally
and consequently only one V
REF
voltage can be used
within each bank. All V
REF
pins in the bank, however, must
be connected to the external voltage source for correct
operation.
Within a bank, inputs that require V
REF
can be mixed with
those that do not. However, only one V
REF
voltage may be
used within a bank. Input buffers that use V
REF
are not 5 V
tolerant. LVTTL, LVCMOS2, and PCI 33 MHz 5 V, are 5 V
tolerant.
The V
CCO
and V
REF
pins for each bank appear in the
device pin-out tables and diagrams. The diagrams also
show the bank affiliation of each I/O.
Within a given package, the number of V
REF
and V
CCO
pins
can vary depending on the size of device. In larger devices,
more I/O pins convert to V
REF
pins. Since these are always
a superset of the V
REF
pins used for smaller devices, it is
possible to design a PCB that permits migration to a larger
device if necessary. All the V
REF
pins for the largest device
anticipated must be connected to the V
REF
voltage, and not
used for I/O.
In smaller devices, some V
CCO
pins used in larger devices
do not connect within the package. These unconnected
pins may be left unconnected externally, or may be con-
nected to the V
CCO
voltage to permit migration to a larger
device if necessary.
In TQ144 and PQ/HQ240 packages, all V
CCO
pins are
bonded together internally, and consequently the same
V
CCO
voltage must be connected to all of them. In the
CS144 package, bank pairs that share a side are intercon-
nected internally, permitting four choices for VCCO. In both
cases, the V
REF
pins remain internally connected as eight
banks, and may be used as described previously.
Configurable Logic Block
The basic building block of the Virtex CLB is the logic cell
(LC). An LC includes a 4-input function generator, carry
logic, and a storage element. The output from the function
generator in each LC drives both the CLB output and the D
input of the flip-flop. Each Virtex CLB contains four LCs,
organized in two similar slices, as shown in
Figure 4
.
Figure 5
shows a more detailed view of a single slice.
In addition to the four basic LCs, the Virtex CLB contains
logic that combines function generators to provide func-
tions of five or six inputs. Consequently, when estimating
the number of system gates provided by a given device,
each CLB counts as 4.5 LCs.
Look-Up Tables
Virtex function generators are implemented as 4-input
look-up tables (LUTs). In addition to operating as a function
generator, each LUT can provide a 16 x 1-bit synchronous
RAM. Furthermore, the two LUTs within a slice can be
combined to create a 16 x 2-bit or 32 x 1-bit synchronous
RAM, or a 16x1-bit dual-port synchronous RAM.
The Virtex LUT can also provide a 16-bit shift register that
is ideal for capturing high-speed or burst-mode data. This
mode can also be used to store data in applications such
as Digital Signal Processing.
Storage Elements
The storage elements in the Virtex slice can be configured
either as edge-triggered D-type flip-flops or as level-sensi-
tive latches. The D inputs can be driven either by the func-
tion generators within the slice or directly from slice inputs,
bypassing the function generators.
In addition to Clock and Clock Enable signals, each Slice
has synchronous set and reset signals (SR and BY). SR
forces a storage element into the initialization state speci-
fied for it in the configuration. BY forces it into the opposite
state. Alternatively, these signals may be configured to
operate asynchronously. All of the control signals are inde-
pendently invertible, and are shared by the two flip-flops
within the slice.
V
CCO
3.3 V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,
GTL+
2.5 V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+
1.5 V HSTL I, HSTL III, HSTL IV, GTL, GTL+
Compatible Standards
X8778_b
Bank 0
GCLK3 GCLK2
GCLK1 GCLK0
Bank 1
Bank 5
Bank 4
Virtex
Device
B
B
B
B
Figure 3: Virtex I/O Banks
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