參數(shù)資料
型號： XCV405E-7FG676I
廠商： Xilinx Inc
文件頁數(shù)： 75/118頁
文件大?。?/td> 0K
描述： IC FPGA 1.8V 676-BGA
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝： 1
系列： Virtex®-E EM
LAB/CLB數(shù)： 2400
邏輯元件/單元數(shù)： 10800
RAM 位總計(jì)： 573440
輸入/輸出數(shù)： 404
門數(shù)： 129600
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 676-BGA
供應(yīng)商設(shè)備封裝： 676-FBGA（27x27）
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
2
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
In addition to the CLK and CE control signals, the three
flip-flops share a Set/Reset (SR). For each flip-flop, this sig-
nal can be independently configured as a synchronous Set,
a synchronous Reset, an asynchronous Preset, or an asyn-
chronous Clear.
The output buffer and all of the IOB control signals have
independent polarity controls.
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. After
configuration, clamping diodes are connected to VCCO with
the exception of LVCMOS18, LVCMOS25, GTL, GTL+,
LVDS, and LVPECL.
Optional pull-up, pull-down and weak-keeper circuits are
attached to each pad. Prior to configuration all outputs not
involved in configuration are forced into their high-imped-
ance state. The pull-down resistors and the weak-keeper
circuits are inactive, but IOs can optionally be pulled up.
The activation of pull-up resistors prior to configuration is
controlled on a global basis by the configuration mode pins.
If the pull-up resistors are not activated, all the pins are in a
high-impedance state. Consequently, external pull-up or
pull-down resistors must be provided on pins required to be
at a well-defined logic level prior to configuration.
All Virtex-E IOBs support IEEE 1149.1-compatible bound-
ary scan testing.
Input Path
The Virtex-E IOB input path routes the input signal directly
to internal logic and/ or through an optional input flip-flop.
An optional delay element at the D-input of this flip-flop elim-
inates pad-to-pad hold time. The delay is matched to the
internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of the
low-voltage signalling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, VREF. The need to supply VREF imposes
constraints on which standards can be used in close prox-
imity to each other. See "I/O Banking" on page 2.
There are optional pull-up and pull-down resistors at each
user I/O input for use after configuration. Their value is in
the range 50 - 100 k
Ω.
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output signal can be
routed to the buffer directly from the internal logic or through
an optional IOB output flip-flop.
The 3-state control of the output can also be routed directly
from the internal logic or through a flip-flip that provides syn-
chronous enable and disable.
Each output driver can be individually programmed for a
wide range of low-voltage signalling standards. Each output
buffer can source up to 24 mA and sink up to 48 mA. Drive
strength and slew rate controls minimize bus transients.
In most signalling standards, the output High voltage
depends on an externally supplied VCCO voltage. The need
to supply VCCO imposes constraints on which standards
can be used in close proximity to each other. See "I/O Bank-
An optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source sig-
nal, the weak keeper holds the signal in its last state if all
drivers are disabled. Maintaining a valid logic level in this
way eliminates bus chatter.
Since the weak-keeper circuit uses the IOB input buffer to
monitor the input level, an appropriate VREF voltage must be
provided if the signalling standard requires one. The provi-
sion of this voltage must comply with the I/O banking rules.
I/O Banking
Some of the I/O standards described above require VCCO
and/or VREF voltages. These voltages are externally sup-
plied and connected to device pins that serve groups of
Table 1:
Supported I/O Standards
I/O
Standard
Output
VCCO
Input
VCCO
Input
VREF
Board
Termination
Voltage
(VTT)
LVTTL
3.3
N/A
LVCMOS2
2.5
N/A
LVCMOS18
1.8
N/A
SSTL3 I & II
3.3
N/A
1.50
SSTL2 I & II
2.5
N/A
1.25
GTL
N/A
0.80
1.20
GTL+
N/A
1.0
1.50
HSTL I
1.5
N/A
0.75
HSTL III & IV
1.5
N/A
0.90
1.50
CTT
3.3
N/A
1.50
AGP-2X
3.3
N/A
1.32
N/A
PCI33_3
3.3
N/A
PCI66_3
3.3
N/A
BLVDS & LVDS
2.5
N/A
LVPECL
3.3
N/A
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