參數(shù)資料
型號： XCV405E-7FG676I
廠商： Xilinx Inc
文件頁數(shù)： 37/118頁
文件大?。?/td> 0K
描述： IC FPGA 1.8V 676-BGA
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標準包裝： 1
系列： Virtex®-E EM
LAB/CLB數(shù)： 2400
邏輯元件/單元數(shù)： 10800
RAM 位總計： 573440
輸入/輸出數(shù)： 404
門數(shù)： 129600
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 676-BGA
供應(yīng)商設(shè)備封裝： 676-FBGA（27x27）
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v3.0) March 21, 2014
Module 2 of 4
21
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
BUFGDLL Pin Descriptions
Use the BUFGDLL macro as the simplest way to provide
zero propagation delay for a high-fanout on-chip clock from
an external input. This macro uses the IBUFG, CLKDLL and
BUFG primitives to implement the most basic DLL applica-
tion as shown in Figure 24.
This symbol does not provide access to the advanced clock
domain controls or to the clock multiplication or clock divi-
sion features of the DLL. This symbol also does not provide
access to the RST, or LOCKED pins of the DLL. For access
to these features, a designer must use the library DLL prim-
itives described in the following sections.
Source Clock Input — I
The I pin provides the user source clock, the clock signal on
which the DLL operates, to the BUFGDLL. For the BUFG-
DLL macro the source clock frequency must fall in the low
frequency range as specified in the data sheet. The BUFG-
DLL requires an external signal source clock. Therefore,
only an external input port can source the signal that drives
the BUFGDLL I pin.
Clock Output — O
The clock output pin O represents a delay-compensated
version of the source clock (I) signal. This signal, sourced by
a global clock buffer BUFG symbol, takes advantage of the
dedicated global clock routing resources of the device.
The output clock has a 50-50 duty cycle unless you deacti-
vate the duty cycle correction property.
CLKDLL Primitive Pin Descriptions
The library CLKDLL primitives provide access to the com-
plete set of DLL features needed when implementing more
complex applications with the DLL.
Source Clock Input — CLKIN
The CLKIN pin provides the user source clock (the clock
signal on which the DLL operates) to the DLL. The CLKIN
frequency must fall in the ranges specified in the data sheet.
A global clock buffer (BUFG) driven from another CLKDLL,
one of the global clock input buffers (IBUFG), or an
IO_LVDS_DLL pin on the same edge of the device (top or
bottom) must source this clock signal. There are four
IO_LVDS_DLL input pins that can be used as inputs to the
DLLs. This makes a total of eight usable input pins for DLLs
in the Virtex-E family.
Feedback Clock Input — CLKFB
The DLL requires a reference or feedback signal to provide
the delay-compensated output. Connect only the CLK0 or
CLK2X DLL outputs to the feedback clock input (CLKFB)
pin to provide the necessary feedback to the DLL. The feed-
back clock input can also be provided through one of the fol-
lowing pins.
IBUFG - Global Clock Input Pad
IO_LVDS_DLL - the pin adjacent to IBUFG
If an IBUFG sources the CLKFB pin, the following special
rules apply.
1.
An external input port must source the signal that drives
the IBUFG I pin.
2.
The CLK2X output must feedback to the device if both
the CLK0 and CLK2X outputs are driving off chip
devices.
3.
That signal must directly drive only OBUFs and nothing
else.
These rules enable the software determine which DLL clock
output sources the CLKFB pin.
Reset Input — RST
When the reset pin RST activates the LOCKED signal deac-
tivates within four source clock cycles. The RST pin, active
High, must either connect to a dynamic signal or tied to
ground. As the DLL delay taps reset to zero, glitches can
occur on the DLL clock output pins. Activation of the RST
pin can also severely affect the duty cycle of the clock out-
put pins. Furthermore, the DLL output clocks no longer
de-skew with respect to one another. For these reasons,
rarely use the reset pin unless re-configuring the device or
changing the input frequency.
2x Clock Output — CLK2X
The output pin CLK2X provides a frequency-doubled clock
with an automatic 50/50 duty-cycle correction. Until the
CLKDLL has achieved lock, the CLK2X output appears as a
1x version of the input clock with a 25/75 duty cycle. This
behavior allows the DLL to lock on the correct edge with
respect to source clock. This pin is not available on the CLK-
DLLHF primitive.
Clock Divide Output — CLKDV
The clock divide output pin CLKDV provides a lower fre-
quency version of the source clock. The CLKDV_DIVIDE
property controls CLKDV such that the source clock is
divided by N where N is either 1.5, 2, 2.5, 3, 4, 5, 8, or 16.
This feature provides automatic duty cycle correction such
that the CLKDV output pin always has a 50/50 duty cycle,
with the exception of noninteger divides in HF mode, where
the duty cycle is 1/3 for N=1.5 and 2/5 for N=2.5.
Figure 24: BUFGDLL Schematic
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
CLKIN
CLKFB
RST
ds022_28_121099
CLKDLL
BUFG
IBUFG
O
I
O
I
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XCV405E-7FG900C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
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XCV405E-8BG404I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
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