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參數(shù)資料
| 型號： | XC6VCX130T-2FFG784I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 1/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA VIRTEX 6 128K 784FFGBGA |
| 產(chǎn)品培訓(xùn)模塊： | Virtex-6 FPGA Overview |
| 產(chǎn)品變化通告： | Virtex-6 FIFO Input Logic Reset 18/Apr/2011 |
| 標準包裝： | 1 |
| 系列： | Virtex® 6 CXT |
| LAB/CLB數(shù)： | 10000 |
| 邏輯元件/單元數(shù)： | 128000 |
| RAM 位總計： | 9732096 |
| 輸入/輸出數(shù)： | 400 |
| 電源電壓： | 0.95 V ~ 1.05 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 784-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 784-FCBGA |
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DS153 (v1.6) February 11, 2011
Product Specification
1
2009–2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
General Description
Virtex-6 CXT FPGAs provide designers needing power-optimized 3.75 Gb/s transceiver performance with an optimized
ratio of built-in system-level blocks. These include 36 Kb block RAM/FIFOs, up to 15 Mb of block RAM, up to 768 DSP48E1
slices, enhanced mixed-mode clock management blocks, PCI Express (GEN 1) compatible integrated blocks, a tri-mode
Ethernet media access controller (MAC), up to 241K logic cells, and strong IP support. Using the third generation ASMBL
(Advanced Silicon Modular Block) column-based architecture, the Virtex-6 CXT family also contains SelectIO technology
with built-in digitally controlled impedance, ChipSync source-synchronous interface blocks, enhanced mixed-mode clock
management blocks, and advanced configuration options. Customers needing higher transceiver speeds, greater I/O
performance, additional Ethernet MACs, or greater capacity should instead use the Virtex-6 LXT or SXT families. Built on a
40 nm state-of-the-art copper process technology, Virtex-6 CXT FPGAs are a programmable alternative to custom ASIC
technology. Virtex-6 CXT FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver
integrated software and hardware components to enable designers to focus on innovation as soon as their development
cycle begins.
Summary of Virtex-6 CXT FPGA Features
Advanced, high-performance, FPGA Logic
Real 6-input look-up table (LUT) technology
Dual LUT5 (5-input LUT) option
LUT/dual flip-flop pair for applications requiring rich
register mix
Improved routing efficiency
64-bit (or 32 x 2-bit) distributed LUT RAM option
SRL32/dual SRL16 with registered outputs option
Powerful mixed-mode clock managers (MMCM)
MMCM blocks provide zero-delay buffering, frequency
synthesis, clock-phase shifting, input-jitter filtering, and
phase-matched clock division
36-Kb block RAM/FIFOs
Dual-port RAM blocks
Programmable
-
Dual-port widths up to 36 bits
-
Simple dual-port widths up to 72 bits
Enhanced programmable FIFO logic
Built-in optional error-correction circuitry
Optionally use each block as two independent 18 Kb
blocks
High-performance parallel SelectIO technology
1.2 to 2.5V I/O operation
Source-synchronous interfacing using
ChipSync technology
Digitally controlled impedance (DCI) active termination
Flexible fine-grained I/O banking
High-speed memory interface support with integrated
write-leveling capability
Advanced DSP48E1 slices
25 x 18, two's complement multiplier/accumulator
Optional pipelining
New optional pre-adder to assist filtering applications
Optional bitwise logic functionality
Dedicated cascade connections
Flexible configuration options
SPI and Parallel Flash interface
Multi-bitstream support with dedicated fallback
reconfiguration logic
Automatic bus width detection
Integrated interface blocks for PCI Express designs
Compliant to the PCI Express Base Specification 2.0
Gen1 Endpoint (2.5 Gb/s) support with GTX transceivers
x1, x2, x4, or x8 lane support per block
One virtual channel, eight traffic classes
GTX transceivers: 150 Mb/s to 3.75 Gb/s
Integrated 10/100/1000 Mb/s Ethernet MAC block
Supports 1000BASE-X PCS/PMA and SGMII using
GTX transceivers
Supports MII, GMII, and RGMII using SelectIO
technology resources
40 nm copper CMOS process technology
1.0V core voltage
Two speed grades (-1 and -2)
Two temperature grades (commercial and industrial)
High signal-integrity flip-chip packaging available in standard
or Pb-free package options
Compatibility across sub-families: CXT, LXT, and SXT
devices are footprint compatible in the same package
52
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC6VCX195T | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-6 CXT Family Data Sheet |
| XC6VCX195T-1FF1156C | 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 199680 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 195K 1156BGA |
| XC6VCX195T-1FF1156I | 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 199680 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 195K 1156BGA |
| XC6VCX195T-1FF784C | 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 199680 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 195K 784BGA |
| XC6VCX195T-1FF784I | 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 199680 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 195K 784BGA |
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