參數(shù)資料
型號： XC6VCX130T-2FFG784I
廠商： Xilinx Inc
文件頁數(shù)： 9/52頁
文件大?。?/td> 0K
描述： IC FPGA VIRTEX 6 128K 784FFGBGA
產(chǎn)品培訓(xùn)模塊： Virtex-6 FPGA Overview
產(chǎn)品變化通告： Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標(biāo)準包裝： 1
系列： Virtex® 6 CXT
LAB/CLB數(shù)： 10000
邏輯元件/單元數(shù)： 128000
RAM 位總計： 9732096
輸入/輸出數(shù)： 400
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 784-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 784-FCBGA
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
17
LVPECL DC Specifications (LVPECL_25)
These values are valid when driving a 100
differential load only, i.e., a 100 resistor between the two receiver pins. The
VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode
ranges. Table 19 summarizes the DC output specifications of LVPECL. For more information on using LVPECL
, see the
Virtex-6 FPGA SelectIO Resources User Guide.
eFUSE Read Endurance
Table 20 lists the maximum number of read cycle operations expected. For more information, see the Virtex-6 FPGA
Configuration User Guide.
GTX Transceiver Specifications
GTX Transceiver DC Characteristics
Table 19: LVPECL DC Specifications
Symbol
DC Parameter
Min
Typ
Max
Units
VOH
Output High Voltage
VCC – 1.025
1.545
VCC –0.88
V
VOL
Output Low Voltage
VCC – 1.81
0.795
VCC –1.62
V
VICM
Input Common-Mode Voltage
0.6
–
2.2
V
VIDIFF
Differential Input Voltage(1)(2)
0.100
–
1.5
V
Notes:
1.
Recommended input maximum voltage not to exceed VCCAUX +0.2V.
2.
Recommended input minimum voltage not to go below –0.5V.
Table 20: eFUSE Read Endurance
Symbol
Description
Speed Grade
Units
-3
-2
-1
-1L
DNA_CYCLES
Number of DNA_PORT READ operations or JTAG ISC_DNA read
command operations. Unaffected by SHIFT operations.
30,000,000
Read
Cycles
AES_CYCLES
Number of JTAG FUSE_KEY or FUSE_CNTL read command
operations. Unaffected by SHIFT operations.
30,000,000
Read
Cycles
Table 21: Absolute Maximum Ratings for GTX Transceivers(1)
Symbol
Description
Min
Max
Units
MGTAVCC
Analog supply voltage for the GTX transmitter and receiver circuits relative to
GND
–0.5
1.1
V
MGTAVTT
Analog supply voltage for the GTX transmitter and receiver termination
circuits relative to GND
–0.5
1.32
V
MGTAVTTRCAL
Analog supply voltage for the resistor calibration circuit of the GTX
transceiver column
–0.5
1.32
V
VIN
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage
–0.5
1.32
V
VMGTREFCLK
Reference clock absolute input voltage
–0.5
1.32
V
Notes:
1.
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
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