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參數(shù)資料
| 型號： | XCR3128XL |
| 廠商： | Xilinx, Inc. |
| 英文描述： | CoolRunner XPLA3 CPLD(CoolRunner XPLA3復(fù)雜可編程邏輯器件) |
| 中文描述： | 的CoolRunner CPLD的XPLA3（的CoolRunner XPLA3復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 109K |
| 代理商： | XCR3128XL |
R
3V, In-System Programming (ISP)
XPLA3 allows for 3V, in-system programming/reprogram-
ming of its EEPROM cells via a JTAG interface. An on-chip
charge pump eliminates the need for externally provided
super-voltages. This allows programming on the circuit
board using only the 3V supply required by the device for
normal operation. The ISP commands implemented in
XPLA3 are specified in
Table 5.
JTAG and ISP Interfacing
A number of industry-established methods exist for
JTAG/ISP interfacing with CPLDs and other integrated cir-
cuits. The XPLA3 family supports the following methods:
Xilinx HW 130
PC Parallel Port
Workstation or PC Serial Port
Embedded Processor
Automated Test Equipment
Third Party Programmers
Xilinx ISP Programming Tools
Table 5:
Low-level ISP Commands
Instruction
(Register Used)
Instruction Code
Description
Enable
(ISP Shift Register)
01001
Enables the Erase, Program, and Verify commands. Using the Enable
instruction before the Erase, Program, and Verify instructions allows the
user to specify the outputs of the device using the JTAG Boundary-Scan
Sample/Preload command.
Erase
(ISP Shift Register)
01010
Erases the entire EEPROM array. User can define the outputs during this
operation by using the JTAG Sample/Preload command.
Program
(ISP Shift Register)
01011
Programs the data in the ISP Shift Register into the addressed EEPROM
row. The outputs can be defined by using the JTAG Sample/Preload
command.
Disable
(ISP Shift Register)
10000
Disable instruction allows the user to leave ISP mode. It selects the ISP
register to be directly connected between TDO and TDI.
Verify
(ISP Shift Register)
01100
Transfers the data from the addressed row to the ISP Shift Register. The
data can then be shifted out and compared with the JEDEC file. The user
can define the outputs during this operation.
Table 6:
Programming Specifications
Symbol
Parameter
Min.
Max.
Unit
DC Parameters
V
CCP
I
CCP
V
IH
V
IL
V
OL
V
OH
AC Parameters
V
CC
supply program/verify
I
CC
limit program/verify
Input voltage (High)
3.0
3.6
V
-
20
mA
2.0
-
V
Input voltage (Low)
-
0.8
V
Output voltage (Low)
-
0.4
V
Output voltage (High)
2.4
-
V
F
MAX
P
WE
P
WP
P
WV
TCK maximum frequency
-
10
MHz
Pulse width erase
100
-
ms
Pulse width program
10
-
ms
Pulse width verify
10
-
μ
s
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3128XL-10CS144C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays 制造商:Xilinx 功能描述:XLXXCR3128XL-10CS144C IC SYSTEM GATE |
| XCR3128XL-10CS144I | 制造商:Xilinx 功能描述:XLXXCR3128XL-10CS144I IC SYSTEM GATE 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3128XL-10CS144I-STI | 制造商:Xilinx 功能描述: |
| XCR3128XL-10CSG144C | 制造商:Xilinx 功能描述: 制造商:Xilinx 功能描述:XLXXCR3128XL-10CSG144C IC SYSTEM GATE 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3128XL-10CSG144I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
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