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參數(shù)資料
| 型號(hào)： | XCR3128XL |
| 廠商： | Xilinx, Inc. |
| 英文描述： | CoolRunner XPLA3 CPLD(CoolRunner XPLA3復(fù)雜可編程邏輯器件) |
| 中文描述： | 的CoolRunner CPLD的XPLA3（的CoolRunner XPLA3復(fù)雜可編程邏輯器件） |
| 文件頁(yè)數(shù)： | 2/10頁(yè) |
| 文件大?。?/td> | 109K |
| 代理商： | XCR3128XL |
CoolRunner
XPLA3 CPLD
2
1-800-255-7778Advance Product SpecificationR
Family Overview
The CoolRunner XPLA3 (eXtended Programmable Logic
Array) family of CPLDs is targeted for low power systems
that include portable, handheld, and power sensitive appli-
cations. Each member of the XPLA3 family includes Fast
Zero Power (FZP) design technology that combines low
power and high speed. With this design technique, the
XPLA3 family offers true pin-to-pin speeds of 5.0 ns, while
simultaneously delivering power that is less than 100
μ
A at
standby without the need for "turbo bits" or other power
down schemes. By replacing conventional sense amplifier
methods for implementing product terms (a technique that
has been used in PLDs since the bipolar era) with a cas-
caded chain of pure CMOS gates, the dynamic power is
also substantially lower than any other CPLD. CoolRunner
devices are the only TotalCMOS PLDs, as they use both a
CMOS process technology and the patented full CMOS
FZP design technique.
The CoolRunner XPLA3 family employs a full PLA structure
for logic allocation within a function block. The PLA pro-
vides maximum flexibility and logic density, with superior pin
locking capability, while maintaining deterministic timing.
XPLA3 CPLDs are supported by WebPACK and WebFIT-
TER from Xilinx and industry standard CAE tools
(Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys,
Viewlogic, andd Synplicity), using text (ABEL, VHDL, Ver-
ilog) and schematic capture design entry. Design verifica-
tion uses industry standard simulators for functional and
timing simulation. Development is supported on personal
computer, Sparc, and HP platforms.
The XPLA3 family features also include industry-standard,
IEEE 1149.1, JTAG interface through which boundary-scan
testing and In-System Programming (ISP) and reprogram-
ming of the device can occur. The XPLA3 CPLD is electri-
cally reprogrammable using industry standard device
programmers.
XPLA3 Architecture
Figure 1
shows a high-level block diagram of a 128 macro-
cell device implementing the XPLA3 architecture. The
XPLA3 architecture consists of function blocks that are
interconnected by a Zero-power Interconnect Array (ZIA).
has 36 inputs from the ZIA and contains 16 macrocells.
From this point of view, this architecture looks like many
other CPLD architectures. What makes the XPLA3 family
unique is logic allocation inside each function block and the
design technique used to implement product terms.
Function Block Architecture
Figure 3
illustrates the function block architecture. Each
function block contains a PLA array that generates control
terms, clock terms, and logic cells. A PLA differs from a PAL
in that the PLA has a fully programmable AND array fol-
lowed by a fully programmable OR array. A PAL array has a
fixed OR array, limiting flexibility. Refer to
Figure 2
for an
example of a PAL and a PLA array. The PLA array receives
its inputs directly from the ZIA. There are 36 pairs of true
and complement inputs from the ZIA that feed the 48 prod-
uct terms in the array. Within the 48 P-terms there are eight
local control terms (LCT[0:7]) available as control signals to
each macrocell for use as asynchronous clocks, resets, pre-
sets and output enables. If not needed as control terms,
these P-Terms can join the other 40 P-Terms as additional
logic resources.
In each function block there are eight foldback NAND prod-
uct terms that can be used to synthesize increased logic
density in support of wider logic equations. This feature can
be disabled in software by the user. As with unused control
P-Terms, unused foldback NAND P-Terms can be used as
additional logic resources.
Sixteen high-speed P-Terms are available at each macro-
cell for speed critical logic. If wider than a single P-Term
logic is required at a macrocell, 47 additional P-Terms can
be summed in prior to the VFM (Variable Function Multi-
plexer). The VFM increases logic optimization by imple-
menting some two input logic funtions before entering the
macrocell (see
Figure 4
).
Each macrocell can support combinatorial or registered
logic. The macrocell register accommodates asynchronous
presets and resets, and "power on" initial state. A hardware
clock enable is also provided for either D or T type registers,
and the register clock input is used as a latch enable when
the macrocell register is configured as a latch function.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCR3256XL-12TQ144I | Connector |
| XCR3256XL-7CS280C | 256 Macrocell CPLD |
| XCR3256XL-7CS280I | Connector |
| XCR3256XL-7FT256C | 256 Macrocell CPLD |
| XCR3256XL-7FT256I | 256 Macrocell CPLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3128XL-10CS144C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays 制造商:Xilinx 功能描述:XLXXCR3128XL-10CS144C IC SYSTEM GATE |
| XCR3128XL-10CS144I | 制造商:Xilinx 功能描述:XLXXCR3128XL-10CS144I IC SYSTEM GATE 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3128XL-10CS144I-STI | 制造商:Xilinx 功能描述: |
| XCR3128XL-10CSG144C | 制造商:Xilinx 功能描述: 制造商:Xilinx 功能描述:XLXXCR3128XL-10CSG144C IC SYSTEM GATE 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3128XL-10CSG144I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
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