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參數(shù)資料
| 型號： | XCR3128XL |
| 廠商： | Xilinx, Inc. |
| 英文描述： | CoolRunner XPLA3 CPLD(CoolRunner XPLA3復(fù)雜可編程邏輯器件) |
| 中文描述： | 的CoolRunner CPLD的XPLA3（的CoolRunner XPLA3復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 109K |
| 代理商： | XCR3128XL |
implemented in the buried macrocell can be fed back to the
ZIA via the macrocell feedback path.
If a macrocell pin is configured as a registered input, there is
a direct path to the register to provide a fast input setup
time. If the macrocell is configured as a latch, the register
clock input functions as the latch enable, with the latch
transparent when this signal is high. The hard-wired clock
enable is non-functional when the macrocell is configured
as a latch.
I/O Cell
The OE (Output Enable) multiplexer has eight possible
modes (
Figure 6
). When the I/O Cell is configured as an
input, a half latch feature exists. This half latch pulls the
input high (through a weak pullup) if the input should float
and cross the threshold. This protects the input from stay-
ing in the linear region and causing an increased amount of
power consumption. This same weak pull up can be
enabled in software such that it is always on when the I/O
Cell is configured as an input. This weak pull up is automat-
ically turned on when a pin is unused by the design.
The I/O Cell is 5V tolerant when the device is powered.
Each output has independent slew rate control (fast or slow)
which will assist in reducing EMI emissions.
Outputs are 3.3V PCI electrical specification compatible (no
internal clamp diode).
Note that an I/O macrocell used as buried logic that does
not have the I/O pin used for input is considered to be
unused, and the weak pull-up resistors will be turned on. It
is recommended that any unused I/O pins on the XPLA3
family of CPLDs be left unconnected. Dedicated input pins
(CLKx/INx) do not have on-chip weak pull-up resistors;
therefore unused dedicated input pins must have external
termination. As with all CMOS devices, do not allow inputs
to float.
Figure 5:
XPLA3 Macrocell Architecture
Global CLK
Global CLK
Universal CLK
P-term CLK
CT [4:7]
ds012_05_122299
Universal PST
CT [0:5]
Universal RST
CT [0:5]
To ZIA
To I/O
PAD
Note:
Global CLK signals come from pins.
To ZIA
VFM
RST
PST
D/T/L
CLKEn
Q
CT4
P-term
48
PLA OR Term
From PT Array
1
Figure 6:
I/O Cell
GND (Weak P.U.)
V
CC
Universal OE
CT
GND
OE [2:0]
To Macrocell / ZIA
From Macrocell
I/O Pin
WP
Slew
Control
OE
Decode
0
1
2
3
4
5
6
7
I/O Pin
State
3-State
Function CT0
Function CT1
Function CT2
Function CT6
Universal OE
Enable
Weak P.U.
ds012_06_121699
Weak Pull-up
OE = 7
V
CC
3
4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3128XL-10CS144C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays 制造商:Xilinx 功能描述:XLXXCR3128XL-10CS144C IC SYSTEM GATE |
| XCR3128XL-10CS144I | 制造商:Xilinx 功能描述:XLXXCR3128XL-10CS144I IC SYSTEM GATE 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3128XL-10CS144I-STI | 制造商:Xilinx 功能描述: |
| XCR3128XL-10CSG144C | 制造商:Xilinx 功能描述: 制造商:Xilinx 功能描述:XLXXCR3128XL-10CSG144C IC SYSTEM GATE 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3128XL-10CSG144I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
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